Nanosheet devices with hybrid structures and methods of fabricating the same
A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.
1. A semiconductor structure, comprising:
a first stack of active channel layers disposed over a semiconductor substrate;
a second stack of active channel layers disposed over the semiconductor substrate;
a dummy channel layer disposed within the second stack, wherein the first stack is free of any dummy channel layer;
a gate structure engaged with the first stack and the second stack; and
first source/drain (S/D) features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, wherein the second S/D features overlap with the dummy channel layer.
2. The semiconductor structure of claim 1 , wherein the first stack includes a first number of active channel layers, the second stack includes a second number of active channel layers, and the second stack includes a third number of the dummy channel layers, and wherein a sum of the second number and the third number is equal to the first number.
3. The semiconductor structure of claim 2 , wherein the third number ranges from one to one less than the first number.
4. The semiconductor structure of claim 1 , wherein the dummy channel layer includes a first dopant species and the second S/D features include a second dopant species that has a conductivity type different from that of the first dopant species.
5. The semiconductor structure of claim 1 , wherein the dummy channel layer includes a semiconductor material doped with a p-type dopant or an n-type dopant, and wherein each active channel layer in the first stack and the second stack is free of any dopant.
6. The semiconductor structure of claim 1 , wherein the first S/D features and the second S/D features each include a doped semiconductor layer and have the same depth.
7. The semiconductor structure of claim 6 , wherein the doped semiconductor layer of the second S/D features overlaps with the dummy channel layer.
8. The semiconductor structure of claim 1 , wherein the first S/D features include a first doped semiconductor layer disposed over an un-doped semiconductor layer and the second S/D features include a second doped semiconductor layer disposed over the un-doped semiconductor layer, and wherein the first doped semiconductor layer extends to below the second doped semiconductor layer.
9. The semiconductor structure of claim 8 , wherein the un-doped semiconductor layer in the second S/D features overlaps with the dummy channel layer.
10. A semiconductor structure, comprising:
a first fin structure including a first stack of active channel layers and protruding from a substrate;
a second fin structure including a second stack of active channel layers disposed over at least one dummy channel layer and protruding from the substrate;
a gate structure engaged with the first stack and the second stack;
a first source/drain (S/D) feature disposed in the first fin structure and adjacent to the first stack, wherein the first S/D feature includes a first doped epitaxial layer over an un-doped epitaxial layer; and
a second S/D feature disposed in the second fin structure and adjacent to the second stack, wherein the second S/D feature includes a second doped epitaxial layer over the un-doped epitaxial layer, and wherein the un-doped epitaxial layer overlaps with the at least one dummy channel layer.
11. The semiconductor structure of claim 10 , wherein the at least one dummy channel layer includes a first dopant and the second S/D feature includes a second dopant, and wherein the first dopant and the second dopant differ in conductivity type.
12. The semiconductor structure of claim 10 , wherein a total number of the at least one dummy channel layer and the active channel layers in the second stack is the same as a total number of the active channel layers in the first stack.
13. The semiconductor structure of claim 10 , further comprising:
a third fin structure including a third stack of active channel layers and protruding from the substrate, wherein the first stack and the third stack include the same number of the active channel layers; and
a third S/D feature disposed in the third fin structure and adjacent to the first stack, wherein the third S/D feature includes a third doped epitaxial layer over the un-doped epitaxial layer, and wherein the first S/D feature extends to below the third S/D feature.
14. The semiconductor structure of claim 13 , wherein a first number of the active channel layers in the first stack that overlap with the first S/D feature is greater than a second number of the active channel layers in the third stack that overlap with the third S/D feature.
15. The semiconductor structure of claim 13 , wherein an offset between a bottom surface of the first S/D feature and the third S/D feature is greater than a thickness of the un-doped epitaxial layer.
16. A method, comprising:
providing a semiconductor substrate having a first region and a second region;
forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin includes a first stack of active channel layers and the second fin includes a second stack of active channel layers disposed over at least one dummy channel layer, and wherein the active channel layers and the at least one dummy channel layer have different compositions;
forming a dummy gate stack over the first fin and the second fin;
forming first source/drain (S/D) features in the first fin and second S/D features in the second fin, wherein the second S/D features overlap with the at least one dummy channel layer; and
replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack is formed adjacent to the first S/D features and the second S/D features.
17. The method of claim 16 , wherein forming the first fin and the second fin includes:
forming a sacrificial layer over the semiconductor substrate;
forming a bottommost active channel layer over the sacrificial layer;
selectively performing an implantation process to a portion of the bottommost active channel layer disposed in the second region with respect to a portion of the bottommost active channel layer disposed in the first region;
thereafter, alternatingly forming the sacrificial layers and the active channel layers over the bottommost active channel layer to form a stack; and
patterning the stack to form the first fin and the second fin.
18. The method of claim 16 , wherein a total number of the active channel layers and the at least one dummy channel layer in the second stack is the same as a total number of the active channel layers in the first stack.
19. The method of claim 16 , wherein forming the first S/D features and the second S/D features include:
forming a first S/D recess in the first fin and a second S/D recess in the second fin;
epitaxially growing a first semiconductor layer in the first S/D recess and the second S/D recess, wherein the first semiconductor layer is free of any dopant species, and wherein the first semiconductor layer overlaps with the at least one dummy channel layer; and
epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer includes a dopant species.
20. The method of claim 16 , wherein the active channel layers are free of any dopant species, the at least one dummy channel layer includes a first dopant species, and the second S/D features includes a second dopant species, and wherein the first dopant species and the second dopant species have different conductivity types.