IP Library Patent Application 18129258
Patent Application
App. No. 18/129,258

METAL INSULATOR METAL (MIM) CAPACITOR ARCHITECTURES

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Quick Facts
Patent No.
US None
App. No.
18/129,258
Abstract

Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

Claims (52)

1 . A metal insulator metal (MIM) capacitor, comprising:

a first electrode;

an insulator over the first electrode, wherein the insulator comprises:

a first layer; and

a second layer over the first layer, wherein the first layer has a leakage current that is less than a leakage current of the second layer, and wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer; and

a second electrode over the insulator.

2 . The MIM capacitor of claim 1 , wherein the first layer is a Sr-rich strontium titanium oxide (STO) layer, and the second layer is a Ti-rich STO layer.

3 . The MIM capacitor of claim 1 , wherein one of the first layer or the second layer is a Sr-rich strontium titanium oxide (STO) layer, and the other of the first layer or the second layer is a stoichiometric STO layer.

4 . The MIM capacitor of claim 1 , wherein the first layer has a thickness between approximately 1 nm and approximately 10 nm, and the second layer has a thickness between approximately 5 nm and approximately 30 nm.

5 . The MIM capacitor of claim 1 , wherein the first layer has a dielectric constant of approximately 120, and the second layer has a dielectric constant of greater than 150.

6 . An integrated circuit structure comprising:

a first build-up layer having a trench therein;

a metal insulator metal (MIM) capacitor in the trench, the MIM capacitor comprising:

a first electrode;

an insulator over the first electrode, wherein the insulator comprises titanium and oxygen; and

a second electrode over the insulator; and

a second build-up layer over the first build-up layer and over the MIM capacitor, wherein a portion of the second build-up layer is in the trench.

7 . The integrated circuit structure of claim 6 , wherein the MIM capacitor further comprises a second insulator over the second electrode, wherein the second insulator comprises titanium and oxygen, and a third electrode over the second insulator.

8 . The integrated circuit structure of claim 6 , wherein the first electrode or the second electrode comprises a metal selected from the group consisting of Ru, RuO 2 , Ir, IrO 2 , Mo, Re, Ti, W, and Mo.

9 . The integrated circuit structure of claim 6 , wherein the insulator is a hafnium free insulating layer.

10 . The integrated circuit structure of claim 6 , wherein the insulator has a TiO 2 composition.

11 . A computing device, comprising:

a board; and

a component coupled to the board, the component including a metal-insulator-metal (MIM) capacitor, comprising:

a first electrode;

an insulator over the first electrode, wherein the insulator comprises:

a first layer; and

a second layer over the first layer, wherein the first layer has a leakage current that is less than a leakage current of the second layer, and wherein the second layer has a dielectric constant that is greater than a dielectric constant of the first layer; and

a second electrode over the insulator.

12 . The computing device of claim 11 , further comprising:

a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:

a communication chip coupled to the board.

14 . The computing device of claim 11 , further comprising:

a camera coupled to the board.

15 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

16 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a first build-up layer having a trench therein;

a metal insulator metal (MIM) capacitor in the trench, the MIM capacitor comprising:

a first electrode;

an insulator over the first electrode, wherein the insulator comprises titanium and oxygen; and

a second electrode over the insulator; and

a second build-up layer over the first build-up layer and over the MIM capacitor, wherein a portion of the second build-up layer is in the trench.

17 . The computing device of claim 16 , further comprising:

a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:

a communication chip coupled to the board.

19 . The computing device of claim 16 , further comprising:

a camera coupled to the board.

20 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2023
From: OGUZ, KAAN; LIN, CHIA-CHING; SEN GUPTA, ARNAB; TUNG, I-CHENG; CHANG, SOU-CHI; LEE, SUDARAT; METZ, MATTHEW V.; AVCI, UYGAR E.; CLENDENNING, SCOTT B.; YOUNG, IAN A.
To: INTEL CORPORATION
Reel/Frame 063230/0484 →