IP Library Granted Patent US 12,744,704
Granted Patent B2
US 12,744,704 · App. 18/130,383 · Granted Sep 22, 2026

Network error reporting and recovery with in-line packet processing pipeline

Inventors: Junggun Lee (Los Altos, CA); Anurag Agrawal (Santa Clara, CA); Yi Li (Fremont, CA); Jeremias Blendin (Santa Cruz, CA); Yanfang Le (San Jose, CA)
Assignee: Intel Corporation
H04L41/0681H04L47/115H04L69/22
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,744,704
App. No.
18/130,383
Granted
Sep 22, 2026
Kind
B2
Abstract

An apparatus is described. The apparatus includes electronic circuitry to support multiple flows within a network. The electronic circuitry to determine respective telemetry information for the multiple flows and inject an alarm message into a particular one of the multiple flows upon an alarm condition being reached for the particular one flow. The alarm message includes a multi-bit error code that describes the alarm condition. The multi-bit error code is one of multiple, possible multi-bit error codes.

Claims (30)

1 . An apparatus, comprising:

electronic circuitry to support multiple flows within a network, the electronic circuitry to determine respective telemetry information for the multiple flows and inject an alarm message into a particular one of the multiple flows upon an alarm condition being reached for the particular one flow, the alarm message comprising a multi-bit error code that describes the alarm condition, the multi-bit error code being one of multiple possible multi-bit error codes.

2 . The apparatus of claim 1 wherein the electronic circuitry comprises a packet processing pipeline.

3 . The apparatus of claim 2 wherein the packet processing pipeline is coupled between an ingress media access control circuitry and a switch core.

4 . The apparatus of claim 1 wherein the electronic circuitry is to insert the alarm message into a header of a packet that belongs to the particular one flow.

5 . The apparatus of claim 1 wherein the electronic circuitry is to create a packet to carry the alarm message and inject the packet into the particular one flow.

6 . The apparatus of claim 1 wherein the electronic circuitry is to collect respective telemetry data for the multiple flows and respectively inject the respective telemetry data into the multiple flows.

7 . The apparatus of claim 6 wherein the electronic circuitry is to accumulate the respective telemetry data for a particular other one of the multiple flows with earlier telemetry data that was earlier determined for the particular other one of the multiple flows and received at an ingress media access control interface.

8 . The apparatus of claim 7 wherein the electronic circuitry is to inject the accumulated telemetry data into the particular other one of the multiple flows.

9 . The apparatus of claim 6 wherein the respective telemetry data for a particular other one of the multiple flows comprises telemetry data for a link that transports packets of the particular other one of the multiple flows and multiple other ones of the multiple flows.

10 . An apparatus comprising:

flow end-point processing circuitry to process a flow's packets at an end-point of the flow, the flow end-point processing circuitry to process a packet that belongs to the flow, the packet comprising an alarm message, the alarm message comprising a multi-bit error code that describes an alarm condition that was reached for the flow, the multi-bit error code being one of multiple possible multi-bit error codes, the flow end-point processing circuitry to raise a flag in response to the flow end-point processing circuitry's processing of the packet.

11 . The apparatus of claim 10 wherein the flow end-point processing circuitry is flow destination end-point processing circuitry, the flow destination end-point processing circuitry to alert the flow's source end-point of the alarm message in response to the flag.

12 . The apparatus of claim 10 wherein the flow end-point processing circuitry is flow destination end-point processing circuitry, the flow destination end-point processing circuitry to send a second alarm message to a network management function in response to the flag.

13 . A data center, comprising:

a pool of CPUs;

a pool of memory resources;

a pool of accelerators;

a network communicatively coupling the pool of CPUs, the pool of memory resources and the pool of accelerators, the network comprising a network switch, the network switch comprising a), b), c) and d) below:

a) a switch core;

b) ingress media access control circuitry;

c) egress media access control circuitry, the network switch to support multiple flows that flow into the ingress media access control circuitry, through the switch core and from the egress media access control circuitry; and,

d) electronic circuitry to support the multiple flows, the electronic circuitry to determine respective telemetry data for the multiple flows and inject an alarm message into a particular one of the multiple flows upon an alarm condition being reached for the particular one flow, the alarm message comprising a multi-bit error code that describes the alarm condition, the multi-bit error code being one of multiple possible multi-bit error codes.

14 . The data center of claim 13 wherein the electronic circuitry comprises a packet processing pipeline coupled between the ingress media access control circuitry and the switch core.

15 . The data center of claim 13 wherein the electronic circuitry is to insert the alarm message into a header of a packet that belongs to the particular one flow.

16 . The data center of claim 13 wherein the electronic circuitry is to create a packet to carry the alarm message and inject the packet into the particular one flow.

17 . The data center of claim 16 further comprising flow end-point processing circuitry to process the particular one flow's packets at an end-point of the particular one flow, the flow end-point processing circuitry to process a packet that belongs to the flow and includes the alarm message, the flow end-point processing circuitry to raise a flag in response to the flow end-point processing circuitry's processing of the packet.

18 . The data center of claim 17 wherein the end-point is a source end-point.

19 . The data center of claim 17 wherein the end-point is a destination end-point.

20 . The data center of claim 17 wherein the circuitry comprises a packet processing pipeline.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2026
From: INTEL CORPORATION
To: INTEL PRODUCTS IP LLC
Reel/Frame 075990/0991 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2023
From: LEE, JUNGGUN; AGRAWAL, ANURAG; LI, YI; BLENDIN, JEREMIAS; LE, YANFANG
To: INTEL CORPORATION
Reel/Frame 063390/0759 →
Continuity (1)
Related Publication 20230239196A1 · Jul 27, 2023
References Cited (27)
US 8687629B1 · Kompella et al. · 2014 [cited by applicant]
US 8713220B2 · Agrawal et al. · 2014 [cited by applicant]
US 10728173B1 · Agrawal et al. · 2020 [cited by applicant]
US 10785342B1 · Bhide et al. · 2020 [cited by applicant]
US 10848429B1 · Lee et al. · 2020 [cited by applicant]
US 10931591B2 · Agrawal et al. · 2021 [cited by applicant]
US 11716291B1 · Agrawal et al. · 2023 [cited by applicant]
US 11750526B2 · Li et al. · 2023 [cited by applicant]
US 20190199602A1 · Zhang et al. · 2019 [cited by applicant]
US 20190286512A1 · Grealish et al. · 2019 [cited by applicant]
US 20200265002A1 · Agrawal et al. · 2020 [cited by applicant]
US 20200280518A1 · Lee et al. · 2020 [cited by applicant]
US 20200366618A1 · Agrawal et al. · 2020 [cited by applicant]
US 20210266219A1 · Kim et al. · 2021 [cited by applicant]
US 20210288945A1 · Branscomb · 2021 [cited by applicant]
US 20210328930A1 · Nikolaidis et al. · 2021 [cited by applicant]
US 20220109587A1 · Sapio et al. · 2022 [cited by applicant]
US 20220109639A1 · Agrawal et al. · 2022 [cited by applicant]
US 20220321400A1 · Kodeboyina et al. · 2022 [cited by applicant]
US 20230038749A1 · Bahadur et al. · 2023 [cited by applicant]
US 20230155988A1 · Peri et al. · 2023 [cited by applicant]
CN 113259143A · 2021 [cited by applicant]
EP 4156655A1 · 2023 [cited by examiner]
Katta, Naga, et al., “Clove: Congestion-Aware Load Balancing at the Virtual Edge”, CoNEXT '17, Dec. 12-15, 2017, Incheon, Republic of Korea, 13 pages. [cited by applicant]
The P4.ORG Applications Working Group, “In-band Network Telemetry (INT) Dataplane Specification”, Version 2.1, Nov. 11, 2020, 56 pages. [cited by applicant]
Wikipedia Contributors, “Explicit Congestion Notification”, Wikipedia, The Free Encyclopedia, https://en.wikipedia.org/w/index.php?title=Explicit_Congestion_Notification&oldid=1143671160 (accessed Apr. 2, 2023), 8 pages. [cited by applicant]
International Search Report and Written Opinion for PCT Patent Application No. PCT/US23/79354, Mailed Mar. 6, 2024, 14 pages. [cited by applicant]