Synchronization in a quantum controller with modular and dynamic pulse generation and routing
A quantum controller comprises a first quantum control pulse generation circuit and a second quantum control pulse generation circuit. The first quantum control pulse generation circuit and a second quantum control pulse generation circuit are operable to operate asynchronously during some time intervals of a quantum algorithm and synchronously during other time intervals of the quantum algorithm.
1. A system comprising:
a synchronization management circuit comprising a synchronization register;
a first pulse generation circuit operable to generate a first pulse; and
a second pulse generation circuit operable to generate a second pulse, wherein:
the first pulse generation circuit and the second pulse generation circuit are operable to determine whether the first pulse is to be generated synchronously or asynchronously with respect to a second pulse, and
when the first pulse and the second pulse are generated synchronously, a timing of the generation is based on a state of the synchronization register.
2. The system of claim 1 , wherein the synchronization management circuit comprises a wait time register.
3. The system of claim 2 , wherein the wait time register is set according to how long it takes signals to propagate between the synchronization management circuit and the first pulse generation circuit and/or between the synchronization management circuit and the second pulse generation circuit.
4. The system of claim 1 , wherein:
the first pulse generation circuit is operable to trigger a change of a state of the synchronization management circuit in response to a detection of a particular value in a synchronization field of an instruction, and
the second pulse generation circuit is operable to begin synchronized pulse generation according to the state of the synchronization management circuit.
5. The system of claim 4 , wherein the second pulse generation circuit is operable to wait for a number of clock cycles, according to a grid-step register, if the second pulse generation circuit does not begin synchronized pulse generation.
6. The system of claim 5 , wherein a value stored in the grid-step register is based on an uncertainty in how long it takes signals to propagate between the synchronization management circuit and the second pulse generation circuit and/or between the synchronization management circuit and the first pulse generation circuit.
7. The system of claim 4 , wherein:
the first pulse generation circuit is operable to wait for a next on-grid clock cycle before triggering the change of the state of the synchronization management circuit.
8. The system of claim 7 , wherein an on-grid clock cycle comprises N clock cycles.
9. The system of claim 8 , wherein a value of N is based on a value stored in a grid-step register of the synchronization management circuit.
10. The system of claim 7 , wherein the synchronization management circuit comprises an on-grid register that is in a first state for 1 out of every N clock cycles and is not in the first state for N−1 of every N clock cycles, where:
N is an integer; and
the next on-grid clock cycle is a next clock cycle in which the on-grid register is in the first state.
11. A system comprising:
a synchronization management circuit comprising a synchronization register;
a first pulse generation circuit operable to generate a first pulse; and
a second pulse generation circuit operable to generate a second pulse, wherein:
the first pulse generation circuit and the second pulse generation circuit are operable to determine whether the first pulse is to be generated synchronously or asynchronously with respect to a second pulse,
the first pulse generation circuit and the second pulse generation circuit are operable to wait to begin generating the first pulse and the second pulse synchronously according to the state of the synchronization management circuit, and
the state of the synchronization management circuit indicates both the first pulse generation circuit and the second pulse generation circuit are ready to begin synchronous operation.
12. The system of claim 11 , wherein the synchronization management circuit comprises a wait time register.
13. The system of claim 12 , wherein the wait time register is set according to how long it takes signals to propagate between the synchronization management circuit and the first pulse generation circuit and/or between the synchronization management circuit and the second pulse generation circuit.
14. The system of claim 11 , wherein:
the first pulse generation circuit is operable to trigger a change of a state of the synchronization management circuit in response to a detection of a particular value in a synchronization field of an instruction, and
the second pulse generation circuit is operable to begin synchronized pulse generation according to the state of the synchronization management circuit.
15. The system of claim 14 , wherein the second pulse generation circuit is operable to wait for a number of clock cycles, according to a grid-step register, if the second pulse generation circuit does not begin synchronized pulse generation.
16. The system of claim 15 , wherein a value stored in the grid-step register is based on an uncertainty in how long it takes signals to propagate between the synchronization management circuit and the second pulse generation circuit and/or between the synchronization management circuit and the first pulse generation circuit.
17. The system of claim 14 , wherein:
the first pulse generation circuit is operable to wait for a next on-grid clock cycle before triggering the change of the state of the synchronization management circuit.
18. The system of claim 17 , wherein an on-grid clock cycle comprises N clock cycles.
19. The system of claim 18 , wherein a value of N is based on a value stored in a grid-step register of the synchronization management circuit.
20. The system of claim 17 , wherein the synchronization management circuit comprises an on-grid register that is in a first state for 1 out of every N clock cycles and is not in the first state for N−1 of every N clock cycles, where:
N is an integer; and
the next on-grid clock cycle is a next clock cycle in which the on-grid register is in the first state.