Three-dimensional memory devices and fabricating methods thereof
Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further includes a second semiconductor structure. The second semiconductor structure includes a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.
1 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a first semiconductor structure, comprising:
forming an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and
forming a slit structure to separate the array of first-type through stack structures from the array of second-type through stack structures;
forming a periphery circuit semiconductor structure, comprising:
forming a first periphery circuit and a second periphery circuit at different levels; and
bonding the periphery circuit semiconductor structure to the first semiconductor structure.
2 . The method of claim 1 , wherein forming the first semiconductor structure further comprises:
forming a semiconductor layer including a first portion on the array of first-type through stack structures and a second portion on the array of second-type through stack structures, wherein the slit structure further separates the first portion of the semiconductor layer from the second portion of the semiconductor layer; and
forming a plurality of vias each penetrating the semiconductor layer and in contact with a corresponding one of the first-type through stack structures or a corresponding one of the second-type through stack structures.
3 . The method of claim 2 , wherein forming the first semiconductor structure further comprises:
forming a dielectric stack including a plurality of interleaved dielectric layers and sacrificial layers stacked on a first substrate;
forming a slit vertically penetrating the dielectric stack and laterally separating the array of first-type through stack structures from the array of second-type through stack structures; and
replacing the plurality of sacrificial layers with a plurality of conductive layers to transform the dielectric stack into a memory stack;
wherein the slit structure is formed to fill the slit.
4 . The method of claim 3 , wherein forming the first-type and second-type through stack structures comprises:
forming a plurality of through stack holes each penetrating the dielectric stack;
filing a first subset of through stack holes in the first region with a sacrificial material;
forming the second-type through stack structures in a second subset of through stack holes in the second region;
removing the sacrificial material in the first subset of through stack holes; and
forming the first-type through stack structures in the first subset of through stack holes.
5 . The method of claim 4 , wherein:
forming the first-type through stack structures comprises forming a FeFET through stack structure; and
forming the second-type through stack structures comprises forming a NAND channel structure FeFET through stack structure.
6 . The method of claim 5 , wherein forming the FeFET through stack structure comprises:
forming a ferroelectric layer on a sidewall of each of the first subset of through stack holes;
forming a conductive layer to cover the ferroelectric layer; and
forming a dielectric filling structure on the ferroelectric layer to fill the first subset of through stack holes.
7 . The method of claim 4 , wherein:
forming the first-type through stack structures comprises forming a FeRAM through stack structure; and
forming the second-type through stack structures comprises forming a NAND channel structure.
8 . The method of claim 7 , wherein forming the FeRAM through stack structure comprises:
forming a ferroelectric layer on a sidewall of each of the first subset of through stack holes; and
forming a conductive filling structure on the ferroelectric layer to fill the first subset of through stack holes.
9 . The method of claim 3 , wherein forming the vias comprises:
forming a plurality of through holes each penetrating the semiconductor layer and exposing a corresponding first type or second-type through stack structure;
filling the through holes with a dielectric material; and
forming the vias each in a corresponding through hole and surrounded by the dielectric material.
10 . The method of claim 9 , further comprising:
forming a plurality of cut structures each laterally extending between the vias and vertically separating portions of the semiconductor layer.
11 . The method of claim 3 , further comprising:
forming a first interconnect layer comprising a plurality of first interconnects in contact with the vias; and
forming a first bonding layer comprising a plurality of first bonding contacts in contact with the first interconnects.
12 . The method of claim 3 , wherein forming the second periphery circuit semiconductor structure, comprising:
forming the first periphery circuit at a first side of a second substrate; and
forming the second periphery circuit on a second semiconductor layer on the first periphery circuit, or at a second side of the second substrate.
13 . The method of claim 12 , wherein forming the first periphery circuit comprises:
forming a main control circuit configured to control the array of first-type through stack structures and the array of second-type through stack structures;
forming a second array periphery circuit configured to operating of the array of second-type through stack structures;
forming a first portion of a first array periphery circuit having a first operating voltage range; and
forming a second portion of the first array periphery circuit having a second operating voltage range higher than the first operating voltage range.
14 . The method of claim 13 , wherein forming the second periphery circuit comprises:
forming a third portion of the first array periphery circuit having a third operating voltage range higher than the second operating voltage range; and
forming a fourth portion of the first array periphery circuit having a fourth operating voltage range higher than the third operating voltage range.
15 . The method of claim 11 , wherein:
forming the periphery circuit semiconductor structure comprises:
forming a second interconnect layer comprising a plurality of second interconnects in contact with a plurality of transistors of the periphery circuit, and
forming a second bonding layer comprising a plurality of second bonding contacts in contact with the second interconnects; and
bonding the periphery circuit semiconductor structure to the first semiconductor structure comprises hybrid bonding the first bonding layer to the second bonding layer, such that each first bonding contact is joined with one corresponding second bonding contact.
16 . A three-dimensional (3D) memory device, comprising:
a first semiconductor structure, comprising:
an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and
a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures;
a periphery circuit semiconductor structure comprising, a first periphery circuit and a second periphery circuit at different levels;
wherein the periphery circuit semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.
17 . The memory device of claim 16 , further comprising:
a semiconductor layer including a first portion on the array of first-type through stack structures and a second portion on the array of second-type through stack structures that are separated by the slit structure; and
a plurality of vias each penetrating the semiconductor layer and in contact with a corresponding one of the first-type through stack structures or the array of second-type through stack structures.
18 . The memory device of claim 16 , wherein:
the first-type through stack structures are FeFET through stack structures; and
the second-type through stack structures are NAND channel structures.
19 . The memory device of claim 18 , wherein each FeFET through stack structure comprises:
a ferroelectric layer;
a conductive layer laterally surrounded by the ferroelectric layer; and
a dielectric filling structure laterally surrounded by the conductive layer.
20 . The memory device of claim 16 , wherein:
the first-type through stack structures are FeRAM through stack structures; and
the second-type through stack structures are NAND channel structures.