Semiconductor device and manufacturing method of the semiconductor device
A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first stack structure penetrated by first channel structures;
forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits;
filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns; and
forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.
2. The method of claim 1 , wherein the first stack structure comprises first material layers and second material layers that are alternately stacked on each other.
3. The method of claim 2 , wherein the second material layers comprise a conductive material, and
wherein the conductive material is separated by the third slits to form lower electrode patterns.
4. The method of claim 2 , further comprising replacing the second material layers of the first stack structure exposed through the third slits with lower electrode patterns, respectively.
5. The method of claim 1 , wherein at least one of the first slits is disposed between the second slits adjacent to each other.
6. The method of claim 1 , wherein each of the first slits has a smaller width than each of the second slits.
7. The method of claim 1 , wherein the first stack structure is divided into first stack patterns by the third slits, and
wherein a distance between the first stack patterns is smaller than a width of each of the second slits.
8. The method of claim 1 , wherein one or more columns of the second channel structures are disposed between the first and second slits adjacent to each other.
9. The method of claim 1 , wherein a number of the second channel structures disposed between the first and second slits adjacent to each other is less than a number of the first channel structures disposed between the third slits adjacent to each other.
10. The method of claim 1 , wherein the first stack structure is divided into first stack patterns by the third slits, and
wherein each of the first stack patterns overlaps two or more electrode patterns disposed in a horizontal direction and separated from each other by at least one of the first slits among the electrode patterns.
11. The method of claim 1 , the forming of the electrode patterns comprises:
forming a second stack structure including a third material layer and a fourth material layer that are alternately stacked on each other on the first stack structure;
forming the second channel structures passing through the second stack structure to be coupled to the first channel structures in a one-to-one manner; and
forming the first slits and the second slits that divide the second stack structure into second stack patterns.
12. The method of claim 11 , wherein the fourth material layer comprises a conductive material included in the electrode patterns.
13. The method of claim 11 , the forming of the electrode patterns further comprises:
removing the fourth material layer of each of the second stack patterns through the first slits and the second slits; and
forming the electrode patterns filling a region from which the fourth material layer is removed and separated from each other by the first slits or the second slits.
14. A semiconductor device, comprising:
a first gate stack structure including first interlayer insulating layers and first electrode patterns that are alternately stacked on each other;
at least one separation insulating layer disposed on the first gate stack structure;
a slit insulating layer disposed on the first gate stack structure;
second gate stack structures each including a second interlayer insulating layer and a second electrode pattern that are alternately stacked on each other, wherein the second gate stack structures are separated from each other by the separation insulating layer and the slit insulating layer; and
a vertical structure passing through the slit insulating layer and the first gate stack structure,
wherein the vertical structure includes an insulating material, and
wherein a width of the slit insulating layer is greater than a width of the vertical structure.
15. The semiconductor device of claim 14 , further comprising:
first channel structures passing through the first gate stack structure; and
second channel structures disposed at both sides of the separation insulating layer, coupled to the first channel structures in a one-to-one manner, and passing through the second gate stack structures.