Memory cell and memory device thereof
A memory cell and a memory device are provided. The memory cell comprises: a write transistor; and a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data; wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable.
1. A memory cell comprising:
a write transistor; and
a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data;
wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable, and the storage node is connected to a control terminal of the read transistor.
2. The memory cell according to claim 1 , wherein
the threshold voltage adjusting layer includes a charge storage layer or a ferroelectric layer; and
the charge storage layer is a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or a floating gate or a floating dot.
3. The memory cell according to claim 1 , wherein
in a read operation, a 0V voltage is applied to a control terminal of the write transistor to turn off the write transistor.
4. The memory cell according to claim 1 , wherein
a channel material of the write transistor includes any one of the following: IGZO, poly-Si, amorphous silicon (a-Si), poly-Ge, a-Ge; and
a channel material of the read transistor includes any one of the following: single crystal Si, single crystal Ge, III-V materials and IGZO.
5. The memory cell according to claim 1 , wherein
the memory cell is a two-dimension monolithic structure,
the write transistor and the read transistor are formed on the same active layer, and
a first terminal of the write transistor is connected to the storage node via a conductive line.
6. The memory cell according to claim 1 , wherein
the memory cell is a three-dimension monolithic stacking structure,
the write transistor is formed on a first tier,
the read transistor is formed on a second tier, and
a conductive line connects between the first tier and the second tier.
7. The memory cell according to claim 1 , wherein
a control terminal of the write transistor and/or the control terminal of the read transistor includes the threshold voltage adjusting layer; and
the threshold voltage of the write transistor is lower than a gate voltage of the write transistor during a write operation; and the threshold voltage of the write transistor is higher than the gate voltage of the write transistor during a read operation or a retention operation.
8. The memory cell according to claim 7 , wherein
the threshold voltage of the read transistor is set that, in the read operation, a first read current in reading logic 1 is higher than a reference current, and a second read current in reading logic 0 is higher than the reference current.
9. A memory device including:
a memory array including a plurality of memory cells, a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines and a plurality of fourth signal lines, the memory cells coupled to the first, the second, the third and the fourth signal lines;
a plurality of driving circuits coupled to the memory array, for applying a plurality of driving voltages to the memory cells via the first, the second, the third and the fourth signal lines to write or read the memory cells; and
a plurality of sensing amplifiers coupled to the memory array, for sensing a plurality of read currents from the memory cells,
wherein each of the memory cells comprising:
a write transistor; and
a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data;
wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable, and the storage node is connected to a control terminal of the read transistor.
10. The memory device according to claim 9 , wherein
the threshold voltage adjusting layer includes a charge storage layer or a ferroelectric layer; and
the charge storage layer is a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or a floating gate or a floating dot.
11. The memory device according to claim 9 , wherein
in a read operation, a 0V voltage is applied to a control terminal of the write transistor to turn off the write transistor.
12. The memory device according to claim 9 , wherein
a channel material of the write transistor includes any one of the following: IGZO, poly-Si, amorphous silicon (a-Si), poly-Ge, a-Ge; and
a channel material of the read transistor includes any one of the following: single crystal Si, single crystal Ge, III-V materials and IGZO.
13. The memory device according to claim 9 , wherein
the memory cell is a two-dimension monolithic structure,
the write transistor and the read transistor are formed on the same active layer, and
a first terminal of the write transistor is connected to the storage node via a conductive line.
14. The memory device according to claim 9 , wherein
the memory cell is a three-dimension monolithic stacking structure,
the write transistor is formed on a first tier,
the read transistor is formed on a second tier, and
a conductive line connects between the first tier and the second tier.
15. The memory device according to claim 9 , wherein
a control terminal of the write transistor and/or the control terminal of the read transistor includes the threshold voltage adjusting layer; and
the threshold voltage of the write transistor is lower than a gate voltage of the write transistor during a write operation; and the threshold voltage of the write transistor is higher than the gate voltage of the write transistor during a read operation or a retention operation.
16. The memory device according to claim 15 , wherein
the threshold voltage of the read transistor is set that, in the read operation, a first read current in reading logic 1 is higher than a reference current, and a second read current in reading logic 0 is higher than the reference current.