Systems and methods for measurement of a parameter of a DUT
Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.
1 . A circuit configured to facilitate measurement of a parameter of a device under test (DUT), the circuit comprising:
a first divider circuit configured to divide a periodic input signal by a first predetermined number so as to generate a first input signal;
a first delay circuit configured to generate a delayed version of the first input signal;
a second divider circuit configured to divide the first input signal by a second predetermined number so as to generate a second input signal; and
a second delay circuit configured to generate different delayed versions of the second input signal, whereby the parameter of the DUT is determined based on the delayed version of the first input signal and the different delayed versions of the second input signal, and
wherein the DUT has a first input connected to an output of the first delay circuit and a second input connected to an output of the second delay circuit and is configured to receive the delayed version of the first input signal as a clock input signal and the different delayed versions of the second input signal as a data input signal, and
wherein the second delay circuit is further configured to receive a variable digital control word and to use the variable digital control word received thereby so as to delay the second input signal different amounts of time.
2 . The circuit of claim 1 , wherein the first delay circuit is further configured to receive a fixed digital control word and to use the fixed digital control word received thereby so as to delay the first input signal a fixed amount of time.
3 . The circuit of claim 1 , wherein the first predetermined number is larger than the second predetermined number.
4 . The circuit of claim 1 , further comprising a first circuit configured to generate first, second, and third digital control words and to use the first, second, and third digital control words generated thereby so as to delay the periodic input signal first, second, and third amounts of time, respectively, wherein the first circuit is further configured to generate a step size based on the first, second, and third digital control words, whereby the parameter of the DUT is determined based further on the step size.
5 . The circuit of claim 4 , wherein the first circuit is further configured to determine a frequency of the periodic input signal and the first circuit generates the step size based further on the frequency of the periodic input signal determined thereby.
6 . A circuit configured to facilitate measurement of a parameter of a device under test (DUT), the circuit comprising:
a divider circuit configured to divide a periodic input signal by a predetermined number so as to generate an input signal;
a first delay circuit configured to generate a delayed version of the input signal;
a second delay circuit configured to generate different delayed versions of the input signal, wherein the delayed version of the input signal and the different delayed versions of the input signal are associated with the parameter of the DUT, wherein the parameter of the DUT is associated with a period of time during which a logic-level of an output of the DUT remains substantially constant between high and low; and
a pulse width modulator (PWM) configured to receive the delayed version of the input signal and the different delayed versions of the input signal and to generate a PWM signal, wherein an input of the DUT is connected to an output of the PWM and configured to receive the PWM signal as a clock input signal,
wherein the second delay circuit is further configured to receive a variable digital control word and to use the variable digital control word received thereby so as to delay the input signal different amounts of time.
7 . The circuit of claim 6 , wherein the PWM is further configured to generate a plurality of PWM signals, each of which has a distinct duty cycle, based on the delayed version of the input signal and the different delayed versions of the input signal, wherein each PWM signal is associated with the parameter of the DUT.
8 . The circuit of claim 7 , wherein the PWM includes one or more logic gates, one or more latch circuits, or a combination thereof.
9 . The circuit of claim 6 , wherein the first delay circuit is further configured to receive a fixed digital control word and to use the fixed digital control word received thereby so as to delay the input signal a fixed amount of time.
10 . The circuit of claim 6 , further comprising a first circuit configured to generate first, second, and third digital control words and to use the first, second, and third digital control words generated thereby so as to delay the periodic input signal first, second, and third amounts of time, respectively, and to generate a step size based on the first, second, and third digital control words, wherein the step size is associated with the parameter of the DUT.
11 . The circuit of claim 10 , wherein the first circuit is further configured to determine a frequency of the periodic input signal and the first circuit generates the step size based further on the frequency of the periodic input signal determined thereby.
12 . A method for facilitating measurement of a parameter of a device under test (DUT), the method comprising:
receiving a periodic input signal;
dividing the periodic input signal by a first predetermined number to generate a first input signal;
dividing the first input signal by a second predetermined number to generate a second input signal;
delaying the first input signal to generate a delayed version of the first input signal;
receiving a variable digital control word;
using the variable digital control word to delay the second input signal different amounts of time; and
delaying the second input signal to generate different delayed versions of the second input signal, wherein the different delayed versions of the second input signal are associated with the parameter of the DUT, the parameter of the DUT is associated with a period of time during which a logic-level of an output of the DUT remains substantially constant between high and low, and the DUT is configured to receive the delayed version of the first input signal as a clock input signal and the different delayed versions of the second input signal as a data input signal.
13 . The method of claim 12 , wherein the delayed version of the first input signal is associated with the parameter of the DUT.
14 . The method of claim 13 , further comprising:
receiving a fixed digital control word; and
using the fixed digital control word to delay the first input signal a fixed amount of time.
15 . The method of claim 12 , wherein the first predetermined number is larger than the second predetermined number.
16 . The method of claim 12 , further comprising:
generating first, second, and third digital control words;
using the first, second, and third digital control words to delay the periodic input signal first, second, and third amounts of time, respectively; and
generating a step size based on the first, second, and third digital control words, wherein the step size is associated with the parameter of the DUT.
17 . The method of claim 16 , further comprising:
determining a frequency of the periodic input signal; and
generating the step size based further on the frequency of the periodic input signal.
18 . The circuit of claim 1 , wherein the first divider circuit, the first delay circuit, the second divider circuit, and the second delay circuit are external to the DUT.
19 . The circuit of claim 18 , wherein the parameter of the DUT is determined based on an output response of the DUT to the delayed version of the first input signal and the different delayed versions of the second input signal.
20 . The method of claim 12 , further comprising:
determining the metastability window based on a difference between (i) a first value of the variable digital control word at which the DUT leaves a metastable state and (ii) a second value of the variable digital control word at which the DUT enters the metastable state.