Systems and methods for duty cycle measurement

1. A method for outputting a duty cycle value of a periodic input signal, the method comprising:

receiving the periodic input signal at a delay circuit configured to delay the periodic input signal based on a digital control word and to generate a delayed version of the periodic input signal, wherein each of the periodic input signal and the delayed version of the periodic input signal includes a plurality of periods, each period having high and low portions;

generating a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal such that a duration of a high or low portion of a period of a first delayed version of the periodic input signal is substantially equal to a total duration of high and low portions of a period of the periodic input signal;

generating a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value;

generating a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value;

calculating a value of a duty cycle of the periodic input signal based on the first, second, and third digital control words; and

outputting the calculated duty cycle value.

2. The method of claim 1 , wherein calculating the value of the duty cycle comprises:

solving an equation

OTW

FULL

-

OTW

LOW

2

×

OTW

FULL

-

OTW

HIGH

-

OTW

LOW

,

where OTW FULL represents the first digital control word, OTW HIGH represents the second digital control word, and OTW LOW represents the third digital control word.

3. The method of claim 1 , wherein the delay circuit is configured to delay the periodic input signal based on a step size representing a minimum amount of delay that can be applied by the delay circuit, the method further comprising:

after determining the duty cycle, using the duty cycle and the first, second, and third digital control words to determine the step size.

4. The method of claim 3 , wherein using the duty cycle and the first, second, and third digital control words to determine the step size comprises:

solving an equation

1

F

DUT

×

(

2

×

OTW

FULL

-

OTW

HIGH

-

OTW

LOW

,

where F DUT represents a frequency corresponding to the duty cycle, OTW FULL represents the first digital control word, OTW HIGH represents the second digital control word, and OTW LOW represents the third digital control word.

5. The method of claim 1 , further comprising:

dividing the periodic input signal by 2 to generate a divided version of the periodic input signal; and

using a phase detector to determine when an edge of the periodic input signal is aligned with an edge of the divided version of the periodic input signal, wherein the alignment of the edges indicates that the periodic input signal has been delayed the first amount of time.

6. The method of claim 1 , further comprising:

generating an inverted version of the periodic input signal; and

using a phase detector to determine when an edge of the periodic input signal is aligned with an edge of the inverted version of the periodic input signal, wherein the alignment of the edges indicates that the periodic input signal has been delayed the second amount of time.

7. The method of claim 1 , further comprising:

inverting the periodic input signal to generate a second signal;

generating an inverted version of the second signal; and

using a phase detector to determine when an edge of the second signal is aligned with an edge of the inverted version of the second signal, wherein the alignment of the edges indicates that the periodic input signal has been delayed the third amount of time.

8. A circuit for outputting a duty cycle value of a periodic input signal comprising:

a delay element configured to delay the periodic input signal based on a digital control word, and to generate a delayed version of the periodic input signal, wherein each of the periodic input signal and the delayed version of the periodic input signal includes a plurality of periods, each period having high and low portions;

a digital circuit configured to

(i) generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal such that a duration of a high or low portion of a period of a first delayed version of the periodic input signal is substantially equal to a total duration of high and low portions of a period of the periodic input signal,

(ii) generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value, and

(iii) generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value; and

a controller configured to calculate a value of a duty cycle of the periodic input signal based on the first, second, and third digital control words and to output the duty cycle value calculated thereby.

9. The circuit of claim 8 , wherein the controller calculating the value of the duty cycle by solving an equation

OTW

FULL

-

OTW

LOW

2

×

OTW

FULL

-

OTW

HIGH

-

OTW

LOW

,

where OTW FULL represents the first digital control word, OTW HIGH represents the second digital control word, and OTW LOW represents the third digital control word.

10. The circuit of claim 8 , wherein

the delay element is configured to delay the periodic input signal based on a step size representing a minimum amount of delay that can be applied by the delay element, and

the controller is configured to determine the step size based on the duty cycle and the first, second, and third digital control words.

11. The circuit of claim 10 , wherein the controller determines the step size by solving an equation

1

F

DUT

×

(

2

×

OTW

FULL

-

OTW

HIGH

-

OTW

LOW

)

,

where F DUT represents a frequency corresponding to the duty cycle, OTW FULL represents the first digital control word, OTW HIGH represents the second digital control word, and OTW LOW represents the third digital control word.

12. The circuit of claim 8 , further comprising:

a divider circuit configured to divide the periodic input signal by 2 to generate a divided version of the periodic input signal; and

a phase detector configured to determine when an edge of the periodic input signal is aligned with an edge of the divided version of the periodic input signal, wherein the alignment of the edges indicates that the periodic input signal has been delayed the first amount of time.

13. The circuit of claim 8 , further comprising:

an inverter configured to generate an inverted version of the periodic input signal; and

a phase detector configured to determine when an edge of the periodic input signal is aligned with an edge of the inverted version of the periodic input signal, wherein the alignment of the edges indicates that the periodic input signal has been delayed the second amount of time.

14. The circuit of claim 8 , further comprising:

one or more inverters configured to (i) invert the periodic input signal to generate a second signal, and (ii) generate an inverted version of the second signal; and

a phase detector configured to determine when an edge of the second signal is aligned with an edge of the inverted version of the second signal, wherein the alignment of the edges indicates that the periodic input signal has been delayed the third amount of time.

15. A circuit for outputting a duty cycle value of a periodic input signal comprising:

a delay locked loop including a delay train and a phase detector, the delay locked loop being configured to receive the periodic input signal;

a digital circuit configured to (i) receive an output of the phase detector indicating an alignment between the periodic input signal and a delayed version of the periodic input signal, and (ii) generate digital control words for controlling an amount of delay applied by the delay train, the digital control words including a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal such that a duration of a high or low portion of a period of a first delayed version of the periodic input signal is substantially equal to a total duration of high and low portions of a period of the periodic input signal, a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value, and a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value; and

a controller configured to calculate a value of a duty cycle of the periodic input signal based on the first, second, and third digital control words and to output the duty cycle value calculated thereby.

16. The circuit of claim 15 , wherein the phase detector includes (i) a first input configured to receive the delayed version of the periodic input signal, and a (ii) a second input configured to receive an inverted version of the periodic input signal.

17. The circuit of claim 15 , further comprising a divider configured to divide the periodic input signal to generate a second periodic signal used in determining the first digital control word.

18. The method of claim 1 , wherein:

in the step of receiving the periodic input signal, receiving the digital control word;

in the step of generating the first digital control word, wherein generating the first digital control word includes generating a waveform that is a slower version of the periodic input signal and aligning an edge of the periodic input signal and an edge of the waveform;

in the step of calculating the value of the duty cycle of the periodic input signal, calculating times the periodic input signal is in high and low states based on the first, second, and third digital control words; and

in the step of outputting the calculated duty cycle value, outputting the calculated times.

19. The circuit of claim 8 , wherein the delay element is configured to receive the periodic input signal and the second digital control word and to generate a second delayed version of the periodic input signal such that a duration of a low portion of the second delayed version of the periodic input signal is substantially equal to a duration of a high portion of the periodic input signal, wherein said low portion of the second delayed version of the periodic input signal is aligned with said high portion of the periodic input signal.

20. The circuit of claim 8 , wherein the delay element is configured to receive the periodic input signal and the third digital control word and to generate a third delayed version of the periodic input signal such that a duration of a high portion of the third delayed version of the periodic input signal is substantially equal to a duration of a low portion of the periodic input signal, wherein said high portion of the third delayed version of the periodic input signal is aligned with said low portion of the periodic input signal.