IP Library Granted Patent US 12,604,672
Granted Patent B2
US 12,604,672 · App. 18/152,178 · Granted Apr 14, 2026

MRAM refill device structure

Inventors: Oscar van der Straten (Guilderland Center, NY); Praneet Adusumilli (Somerset, NJ); Chih-Chao Yang (Glenmont, NY)
Assignee: International Business Machines Corporation
H10N50/80H10B61/00H10N50/01H10N50/20
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Quick Facts
Patent No.
US 12,604,672
App. No.
18/152,178
Granted
Apr 14, 2026
Kind
B2
Abstract

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a dielectric layer on top of a bottom contact; creating an opening in the dielectric layer, the opening has a slant top edge; filling a bottom portion of the opening to form a bottom electrode; filling a top portion of the opening with a first ferromagnetic material to form a first ferromagnetic layer; forming a stack of blanket layers, including a blanket tunnel barrier layer, a blanket second ferromagnetic layer, and a blanket top electrode layer, on top of the first ferromagnetic layer; patterning the stack of blanket layers into a top portion of a magnetic tunnel junction stack that includes a tunnel barrier layer, a second ferromagnetic layer, and a top electrode; and forming a top contact in contact with the top electrode. A structure formed thereby is also provided.

Claims (17)

1 . A magnetoresistive random-access memory (MRAM) structure comprising:

a magnetic tunnel junction (MTJ) stack, the MTJ stack, from a bottom to a top thereof, includes a bottom electrode; a first ferromagnetic layer; a tunnel barrier layer; a second ferromagnetic layer; and a top electrode,

wherein the first ferromagnetic layer has a top surface and a bottom surface, the top surface is larger than the bottom surface, a bottom surface of the tunnel barrier layer is in direct contact with the top surface of the first ferromagnetic layer, and a horizontal size of the bottom surface of the tunnel barrier layer is less than a horizontal size of the top surface of the first ferromagnetic layer.

2 . The MRAM structure of claim 1 , wherein a top portion of the MTJ stack includes the top electrode, the second ferromagnetic layer, and the tunnel barrier layer, and the top portion of the MTJ stack has a slant sidewall and is above the first ferromagnetic layer.

3 . The MRAM structure of claim 2 , wherein the first ferromagnetic layer and the bottom electrode are covered by a first encapsulation layer and the top portion of the MTJ stack is covered by a second encapsulation layer, wherein the first encapsulation layer and the second encapsulation layer are made of different materials.

4 . The MRAM structure of claim 3 , wherein the first encapsulation layer is made of silicon-aluminum-nitride (SiAlN) or silicon-aluminum-oxynitride (SiAlON), and the second encapsulation layer is made of silicon-nitride (SiN) or silicon-carbonitride (SiCN).

5 . The MRAM structure of claim 1 , wherein the top electrode is made of niobium-carbonitride (NbCN) or titanium-carbonitride (TiCN).

6 . The MRAM structure of claim 1 , wherein the first ferromagnetic layer is a reference layer, and the second ferromagnetic layer is a free layer.

7 . The MRAM structure of claim 6 , wherein the reference layer, the tunnel barrier layer, and the free layer form a spindle shape with the tunnel barrier layer at a middle thereof.

8 . A semiconductor structure comprising:

a magnetic tunnel junction (MTJ) stack, the MTJ stack includes a bottom electrode; a reference layer; a tunnel barrier layer; a free layer; and a top electrode;

a first metal level in contact with the bottom electrode of the MTJ stack; and

a second metal level in contact with the top electrode of the MTJ stack,

wherein the reference layer has a top surface and a bottom surface and a slant sidewall, the top surface being larger than the bottom surface and the bottom surface being directly above the bottom electrode; a top portion of the MTJ stack includes the top electrode, the free layer, and the tunnel barrier layer to be above the reference layer; the top portion of the MTJ stack has a slant sidewall; a top surface of the top portion of the MTJ stack is smaller than a bottom surface of the top portion of the MTJ stack; the reference layer and the bottom electrode are covered by a first encapsulation layer and the top portion of the MTJ stack is covered by a second encapsulation layer; and the first encapsulation layer and the second encapsulation layer are made of different materials.

9 . The semiconductor structure of claim 8 , wherein the top electrode is made of niobium-carbonitride (NbCN) or titanium-carbonitride (TiCN).

10 . The semiconductor structure of claim 8 , wherein the reference layer, the tunnel barrier layer, and the free layer form a spindle shape with the tunnel barrier layer at a middle thereof.

11 . The semiconductor structure of claim 8 , wherein the tunnel barrier layer has a top surface and a bottom surface, the bottom surface of the tunnel barrier layer being directly above the reference layer; the free layer has a top surface and a bottom surface, the bottom surface of the free layer being directly above the tunnel barrier layer and the top surface of the free layer being smaller than the bottom surface of the free layer; and the top electrode has a top surface and a bottom surface, the bottom surface of the top electrode being directly above the free layer and the top surface of the top electrode being smaller than the bottom surface of the top electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2023
From: VAN DER STRATEN, OSCAR; ADUSUMILLI, PRANEET; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 062320/0790 →
Continuity (1)
Related Publication 20240237548A1 · Jul 11, 2024
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