IP Library Granted Patent US 12,424,555
Granted Patent B2
US 12,424,555 · App. 18/153,447 · Granted Sep 23, 2025

Semiconductor structure and semiconductor device

Inventor: Yulei Wu (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H01L23/5329H01L21/7682H01L21/76831H01L23/5226H01L23/53214H01L23/564H10B12/50
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Quick Facts
Patent No.
US 12,424,555
App. No.
18/153,447
Granted
Sep 23, 2025
Kind
B2
Abstract

The present disclosure provides a semiconductor structure and a semiconductor device. The semiconductor structure includes a first conductive layer, a first barrier layer, and an insulating layer. The first conductive layer includes at least two traces, and a recess is formed between two adjacent ones of the traces. The first barrier layer is provided on a sidewall of the recess. The insulating layer fills the recess, and an air gap is formed in the insulating layer located in the recess.

Claims (25)

1. A semiconductor structure, comprising:

a first conductive layer comprising at least two first traces, wherein a recess is formed between two adjacent ones of the first traces;

a first barrier layer provided on a sidewall of the recess;

an insulating layer filling the recess, wherein an air gap is formed in the insulating layer located in the recess;

a first dielectric layer provided on a bottom surface of the first conductive layer, wherein the recess runs through the first conductive layer;

a second dielectric layer located below the first dielectric layer;

a second barrier layer provided between the first dielectric layer and the second dielectric layer; and

a second conductive layer comprising a plurality of second traces, wherein the second dielectric layer is provided between two adjacent ones of the second traces, and the second trace is connected to the first conductive layer by a first interconnect structure running through the second barrier layer and the first dielectric layer;

wherein the recess runs through the first dielectric layer and extends to the second barrier layer, and a top surface of the second barrier layer exposed in the recess defines a bottom wall of the recess.

2. The semiconductor structure according to claim 1 , wherein the first barrier layer is further provided on at least one of a top surface of the first conductive layer or a bottom wall of the recess.

3. The semiconductor structure according to claim 1 , wherein along a direction from a top surface of the first conductive layer to a bottom surface of the first conductive layer, an extension length of the air gap is less than a thickness of the first conductive layer.

4. The semiconductor structure according to claim 1 , wherein the recess further runs through the first dielectric layer, and along a direction from a top surface of the first conductive layer to the bottom surface of the first conductive layer, an extension length of the air gap is greater than a thickness of the first conductive layer and less than a sum of thicknesses of the first conductive layer and the first dielectric layer.

5. The semiconductor structure according to claim 1 , wherein the first barrier layer is made of a same material as the second barrier layer.

6. The semiconductor structure according to claim 1 , wherein orthographic projection of the recess on a top surface of the first conductive layer and orthographic projection of the first interconnect structure on the top surface of the first conductive layer are arranged in a staggered manner.

7. The semiconductor structure according to claim 1 , wherein the semiconductor structure further comprises at least one third conductive layer and at least one third barrier layer, the third conductive layer comprises a plurality of third traces and a third dielectric layer, the third dielectric layer is provided between two adjacent ones of the third traces, and the third barrier layer and the third conductive layer are sequentially laminated on one side of the second dielectric layer away from the second conductive layer, wherein

the third conductive layer closest to the second dielectric layer is connected to the second conductive layer by a second interconnect structure running through the second dielectric layer and the third barrier layer, and two adjacent ones of the third conductive layers are connected by a third interconnect structure running through the third barrier layer and the third dielectric layer.

8. The semiconductor structure according to claim 1 , wherein a material of the first barrier layer comprises silicon nitride.

9. The semiconductor structure according to claim 1 , wherein the insulating layer comprises:

a first insulating layer provided on a top surface of the first conductive layer and filling the recess, wherein the air gap is formed in the first insulating layer located in the recess; and

a second insulating layer provided on a top surface of the first insulating layer.

10. The semiconductor structure according to claim 9 , wherein at least one of:

a material of the first insulating layer comprises silicon oxide; or

a material of the second insulating layer comprises silicon nitride.

11. The semiconductor structure according to claim 1 , wherein a material of the first conductive layer comprises aluminum.

12. A semiconductor device, wherein the semiconductor device comprises the semiconductor structure according to claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2023
From: WU, YULEI
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 062356/0123 →
Priority Claims (1)
CN 202111042445.2 · Sep 7, 2021 · national
Continuity (2)
Continuation PCTCN2022110344 · Aug 4, 2022
Related Publication 20230154853A1 · May 18, 2023
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