THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF FORMING THE SAME

1 . A method of forming a memory device, comprising:

forming an alternating stack of disposable material layers and silicon nitride layers over a substrate;

forming a memory opening through the alternating stack;

forming a memory film and a vertical semiconductor channel in the memory opening, wherein the memory film comprises a continuous silicon nitride charge storage material layer and a tunneling dielectric layer;

forming a backside trench through the alternating stack;

forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers through the backside trench;

oxidizing portions of the silicon nitride layers and the continuous silicon nitride charge storage material layer exposed in the laterally-extending cavities to form silicon oxide insulating layers and to separate the continuous silicon nitride charge storage material layer into a vertical stack of discrete silicon nitride charge storage material portions; and

replacing remaining portions of the silicon nitride layers with electrically conductive layers.

2 . The method of claim 1 , wherein:

the portions of the continuous silicon nitride charge storage material layer that are exposed in the laterally-extending cavities are converted into a vertical stack of annular silicon oxide material portions during the oxidizing; and

the vertical stack of discrete silicon nitride charge storage material portions is interlaced with the vertical stack of annular silicon oxide material portions along a vertical direction.

3 . The method of claim 1 , wherein the portions of the silicon nitride layers that are exposed in the laterally-extending cavities are converted into silicon oxide material portions that expand in volume to fill the laterally-extending cavities.

4 . The method of claim 3 , further comprising laterally recessing the silicon oxide material portions, wherein remaining parts of the silicon oxide material portions that fill the laterally-extending cavities comprise the silicon oxide insulating layers.

5 . The method of claim 1 , wherein the memory film further comprises a blocking dielectric layer.

6 . The method of claim 1 , further comprising removing portions of the blocking dielectric layer exposed in the laterally-extending cavities, wherein remaining portions of the blocking dielectric layer comprise a vertical stack of tubular insulating spacers.

7 . The method of claim 1 , wherein the replacing the remaining portions of the silicon nitride layers with the electrically conductive layers comprises selectively removing the remaining portions of the silicon nitride layers through the backside trench to form backside recesses, recessing the silicon oxide insulating layers to remove a bird's beak, and forming the electrically conductive layers in the backside recesses through the backside trench.

8 . The method of claim 1 , wherein a horizontally-extending seam is formed in each of the silicon oxide insulating layers during the oxidation.

9 . The method of claim 1 , wherein an air gap is formed in each of the silicon oxide insulating layers during the oxidation.

10 . The method of claim 1 , wherein the oxidizing comprises a high pressure oxidation step in a water vapor ambient at a pressure of at least 10 atm and a temperature of at least 750 degrees Celsius.

11 . A memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a vertical stack of silicon nitride charge storage material portions, a vertical stack of annular silicon oxide material portions that is interlaced with the vertical stack of silicon nitride charge storage material portions along a vertical direction, and a vertical semiconductor channel,

wherein:

each of the insulating layers has a horizontally-extending seam therein; and

at least one of the insulating layers has an air gap that is adjoined to a respective horizontally-extending seam and laterally surrounding the memory opening fill structure.

12 . The memory device of claim 11 , wherein each of the insulating layers is in direct contact with a respective annular silicon oxide material portion within the vertical stack of annular silicon oxide material portions.

13 . The memory device of claim 11 , wherein each of the insulating layers comprises a silicon oxide material formed by oxidation of silicon nitride layers.

14 . The memory device of claim 11 , wherein the air gap is bounded by and is in contact with an outer surface of a respective annular silicon oxide material portion within the vertical stack of annular silicon oxide material portions.

15 . The memory device of claim 11 , wherein each surface of the annular silicon oxide material portions that contacts a respective one of the silicon nitride charge storage material portions has a convex vertical cross-sectional profile.

16 . The memory device of claim 11 , wherein the memory opening fill structure further comprises a vertical stack of tubular insulating spacers that is interlaced with the insulating layers along the vertical direction.

17 . The memory device of claim 16 , wherein inner cylindrical sidewalls of the tubular insulating spacers contact outer sidewalls of the silicon nitride charge storage material portions.

18 . The memory device of claim 16 , wherein each of the tubular insulating spacers contacts at least one cylindrical outer surface segment of the vertical stack of annular silicon oxide material portions.

19 . The memory device of claim 16 , wherein a subset of the insulating layers comprises a respective pair of convex annular surface segments that contacts concave annular surface segments of a respective pair of the tubular insulating spacers.

20 . The memory device of claim 16 , wherein each of the tubular insulating spacers comprises a blocking dielectric material portion, and wherein a tunneling dielectric layer is located between the vertical semiconductor channel and the interlaced vertical stacks of the silicon nitride charge storage material portions and the annular silicon oxide material portions.