Antenna port termination in absence of power supply
Methods and devices to address antenna termination in absence of power supplies within an electronic circuit including a termination circuit and a switching circuit. The devices include regular NMOS devices that decouple the antenna from the switching circuit in absence of power supplies while the antenna is coupled to a terminating impedance having a desired impedance value through a native NMOS device. The antenna is coupled with the switching circuit via the regular NMOS device during powered conditions while the antenna is decoupled from the terminating impedance.
1. An electronic circuit comprising:
a series arrangement of a first switch and a termination impedance;
a switching circuit including radio frequency (RF) switches;
a second switch coupling an antenna and the series arrangement of the first switch and the termination impedance to the switching circuit;
wherein:
a threshold voltage of the first switch is less than a threshold voltage of the second switch;
in a powered condition, the antenna is connected to the switching circuit and disconnected from the termination impedance, and
in an unpowered condition, the antenna is connected to the termination impedance and disconnected from the switching circuit.
2. The electronic circuit of claim 1 , wherein:
in the powered condition, the first switch is in an OFF state and the second switch is in an ON state, and
in the unpowered condition, the first switch is in the ON state and the second switch is in the OFF state.
3. The electronic circuit of claim 2 , wherein in the powered condition of the electronic circuit, the first switch receives a first supply voltage, and the second switch receives a second supply voltage different from the first supply voltage, and wherein in the unpowered condition of the electronic circuit, the first and the second switches receive zero bias voltages.
4. The electronic circuit of claim 3 , wherein, in the powered condition of the electronic circuit, the first supply voltage is negative, and the second supply voltage is positive.
5. The electronic circuit of claim 4 , wherein the first switch comprises a stack of two or more serially connected transistors.
6. The electronic circuit of claim 5 , wherein the second switch comprises a stack of two more serially connected transistors.
7. The electronic circuit of claim 4 , wherein the second circuit comprises a plurality of single-pole single-throw (SPST) switches.
8. The electronic circuit of claim 7 , wherein each SPST switch of the plurality of SPST switches comprises a through switch and a shunt switch.
9. The electronic circuit of claim 8 , wherein the though switch comprises a through switch stack comprising a plurality of native NMOS serially connected transistors.
10. The electronic circuit of claim 9 , wherein the shunt switch comprises a shunt switch stack comprising a plurality of native NMOS serially connected transistors.
11. The electronic circuit of claim 8 , wherein the through switch comprises a series connection of a first and a second through switch, both connected to a shunt switch.
12. The electronic circuit of claim 11 , wherein each of the first and the second through switch and the shunt switch comprises a plurality of native NMOS serially connected transistors.
13. The electronic circuit of claim 1 , wherein the first switch comprises one or more native NMOS transistors and the second switch comprises one or more regular NMOS transistors.
14. A method of terminating an antenna to a termination impedance, the method comprising:
providing a switching circuit including a plurality of switching transistors;
coupling the antenna to the termination impedance through a first switch, the first switch having a first threshold voltage;
coupling the antenna to the switching circuit through a second switch, the second switch having a second threshold voltage being greater than the first threshold voltage;
in a powered condition, turning the first switch to an OFF state, and the second switch to an ON state, and
in an unpowered condition, turning the first switch to an ON state, and the second switch to an OFF state.
15. The method of claim 14 , further comprising:
in the powered condition, applying a first bias voltage to the first switch, and a second bias voltage to the second switch, the first bias voltage being less than the second bias voltage, and
in the unpowered condition, applying zeros bias voltages to the first and the second switch.
16. The method of claim 15 , wherein the first switch comprises a native NMOS transistor and the second switch comprises a regular NMOS transistor.