Granted Patent B2

US 12,423,505 · App. 18/161,657 · Granted Sep 23, 2025

Inventors: Sheng-Hsiung Chen (Hsinchu, TW); Fong-Yuan Chang (Hsinchu, TW); Ho Che Yu (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

G06F30/398G06F30/392H10B43/50

Abstract

Claims (158)

1. A semiconductor device comprising:

fins representing active regions, the fins extending in a first direction;

gate structures correspondingly over the fins and extending in a second direction perpendicular to the first direction;

the fins being configured to have a first conductivity type (F-fin) or a different second conductivity type (S-fin);

the fins being aligned along tracks and arranged in rows;

a first one of the rows (first row) having a single-row height relative to the second direction, top and bottom boundaries of the first row being aligned with corresponding ones of the tracks;

the first row including an alpha-type (α-type) cell region and a beta-type (β-type) cell region each of which has the single-row height;

the α-type cell region including a first F-fin, a first S-fin and a first gate structure,

top and bottom edges of the α-type cell region being co-track aligned correspondingly with the top and bottom boundaries of the first row and free from being overlapped by the first F-fin or the first S-fin, and

the first gate structure overlapping each of the first F-fin and the first S-fin and being free from overlapping the top and bottom edges of the α-type cell region; and

the β-type cell region including a second F-fin, a second S-fin, a third F-fin, a third S-fin and a second gate structure;

the second gate structure overlapping each of the second F-fin and the second S-fin, and further overlapping at least one of the third F-fin or the third S-fin;

a top edge of the β-type cell region being co-track aligned with the top boundary of the first row and co-track aligned with the third F-fin; and

a bottom edge of the β-type cell region being co-track aligned with the bottom boundary of the first row and co-track aligned with the third S-fin.

2. The semiconductor device of claim 1 , wherein:

the second F-fin of the β-type cell region is co-track aligned with the first F-fin of the α-type cell region; and

the second S-fin of the β-type cell region is co-track aligned with the first S-fin of the α-type cell region.

3. The semiconductor device of claim 1 , wherein:

a second one of the rows (second row) has the single-row height, top and bottom boundaries of the second row being aligned with corresponding ones of the tracks,

relative to the second direction, the second row is stacked on or stacked under the first row, and

the second row includes a third-type (γ-type) cell region which has at least the single-row height;

relative to the first direction, the γ-type cell region is aligned with the β-type cell region;

the γ-type cell region includes at least a fourth F-fin, at least a fourth S-fin and a third gate structure;

regarding top and bottom edges of the γ-type cell region,

the bottom edge of the γ-type cell region is co-track aligned with the top boundary of the first row and free from being overlapped by the fourth F-fin, or

the top edge of the γ-type cell region is co-track aligned with the bottom boundary of the first row and free from being overlapped by the fourth S-fin;

the third gate structure overlaps the fourth F-fin or the fourth S-fin;

at least one of a circumstance (A) or a circumstance (B) is true;

the circumstance (A) being that the second gate structure further overlaps the third F-fin, and the third gate structure is free from overlapping the third F-fin; and

the circumstance (B) being that the second gate structure further overlaps the third S-fin, and the third gate structure is free from overlapping the third S-fin.

4. The semiconductor device of claim 3 , wherein:

the second gate structure further overlaps each of the third F-fin and the third S-fin;

the γ-type cell region is a first γ-type cell region;

relative to the second direction, the second row is stacked on the first row;

the bottom edge of the first γ-type cell region is co-track aligned with the top boundary of the first row and free from being overlapped by the fourth F-fin;

a third one of the rows (third row) has the single-row height, top and bottom boundaries of the third row being aligned with corresponding ones of the tracks;

relative to the second direction, the third row is stacked under the first row; and

the third row includes a second γ-type cell region which has at least the single-row height;

relative to the first direction, the second γ-type cell region is aligned with the β-type cell region;

the second γ-type cell region includes at least a fifth F-fin, at least a fifth S-fin and a third gate structure,

the fifth S-fin being the third S-fin and the fifth F-fin; and

a top edge of the second γ-type cell region being co-track aligned with the bottom boundary of the first row and free from being overlapped by the fifth S-fin;

the third gate structure overlaps the fifth S-fin; and

the third gate structure is free from overlapping the third S-fin.

5. The semiconductor device of claim 1 , wherein:

the second gate structure of the second γ-type cell region further overlaps each of the third F-fin and the third S-fin.

6. The semiconductor device of claim 1 , wherein:

the α-type cell region is a first α-type cell region;

the second gate structure overlaps the third F-fin;

a second one of the rows (second row) has the single-row height, top and bottom boundaries of the second row being aligned with corresponding ones of the tracks;

relative to the second direction, the second row is stacked on the first row;

the second row includes a second α-type cell region which has the single-row height;

relative to the first direction, the second α-type cell region is aligned with the β-type cell region;

the second α-type cell region includes a fourth F-fin, a fourth S-fin and a third gate structure;

a bottom edge of the second α-type cell region is co-track aligned with the top boundary of the first row and free from being overlapped either of the fourth F-fin or the fourth S-fin;

the third gate structure overlaps the fourth F-fin and the fourth S-fin; and

the third gate structure is free from overlapping the third F-fin.

7. The semiconductor device of claim 6 , wherein:

the second gate structure overlaps the third S-fin.

8. The semiconductor device of claim 6 , wherein:

the second gate structure is free from overlapping the third S-fin.

9. The semiconductor device of claim 8 , wherein:

the β-type cell region is a first β-type cell region;

a third one of the rows (third row) has the single-row height, top and bottom boundaries of the second row being aligned with corresponding ones of the tracks;

relative to the second direction, the third row is stacked under the first row;

the third row includes a third-type (γ-type) cell region which has the single-row height;

relative to the first direction, the γ-type cell region is aligned with the β-type cell region;

the γ-type cell region includes at least a fourth F-fin, at least a fourth S-fin and a fourth gate structure;

a top edge of the γ-type cell region is co-track aligned with the bottom boundary of the first row and the fourth S-fin; and

the fourth gate structure overlaps the fourth S-fin.

10. The semiconductor device of claim 1 , wherein:

the α-type cell region is a first α-type cell region;

the second gate structure overlaps the third S-fin;

a second one of the rows (second row) has the single-row height, top and bottom boundaries of the second row being aligned with corresponding ones of the tracks;

relative to the second direction, the second row is stacked on the first row;

the second row includes a third-type (γ-type) cell region which has the single-row height;

relative to the first direction, the γ-type cell region is aligned with the β-type cell region;

the γ-type cell region includes a fourth F-fin, a fourth S-fin and a third gate structure;

a bottom edge of the γ-type cell region is co-track aligned with the top boundary of the first row;

the third gate structure overlaps the fourth F-fin and the fourth S-fin;

either a circumstance (A) or a circumstance (B) is true,

the circumstance (A) being that the bottom edge of the γ-type cell region is free from being overlapped by the third gate structure whereas the top edge of the γ-type cell region is overlapped by the third gate structure; and

the circumstance (B) being that the bottom edge of the γ-type cell region is overlapped by the third gate structure whereas the top edge of the γ-type cell region is free from being overlapped by the third gate structure.

11. The semiconductor device of claim 10 , wherein:

the circumstance (A) is true;

the γ-type cell region further includes a fifth S-fin; and

the fifth S-fin is overlapped by the third gate structure.

12. The semiconductor device of claim 10 , wherein:

the circumstance (B) is true;

the γ-type cell region further includes a fifth F-fin; and

the fifth F-fin is overlapped by the third gate structure.

13. A semiconductor device comprising:

fins representing active regions, the fins extending in a first direction;

gate structures correspondingly over the fins and extending in a second direction perpendicular to the first direction;

the fins being configured to have a first conductivity type (F-fin) or a different second conductivity type (S-fin);

the fins being aligned along tracks and arranged in rows;

each of a first one of the rows (first row) and a second one of the rows (second row) having a single-row height relative to the second direction, top and bottom boundaries correspondingly of each of the first and second rows being aligned with corresponding ones of the tracks;

relative to the second direction, the second row being stacked on the first row; and

a first alpha-type (α-type) cell region having first and second portions correspondingly in the first and second rows such that the first α-type cell region has a double-row height;

the α-type cell region including first, second and third F-fins, first, second and third S-fins and a first gate structure;

a top edge of the α-type cell region being co-track aligned with the top boundary of the second row and free from being overlapped by the first to third F-fins and the first to third S-fins;

a bottom edge of the α-type cell region being co-track aligned correspondingly with the bottom boundary of the first row and being overlapped by the second S-fin;

the top boundary of the second row and the bottom boundary of the first row being co-track aligned and overlapped by the second F-fin; and

the first gate structure overlapping each of the first to third F-fins and the first to third S-fins, and being free from overlapping the top edge of the α-type cell region.

14. The semiconductor device of claim 13 , wherein:

a third one of the rows (third row) has the single-row height, top and bottom boundaries of the second row being aligned with corresponding ones of the tracks;

relative to the second direction, the third row is stacked on the second row,

the second row includes a beta-type (β-type) cell region which has at least the single-row height;

relative to the first direction, the β-type cell region is aligned with the α-type cell region;

the β-type cell region includes at least a fourth F-fin, at least fourth and fifth S-fin and a second gate structure;

a bottom edge of the β-type cell region is co-track aligned with the top boundary of the second row and is the fourth S-fin;

the second gate structure overlaps the fourth F-fin and the fourth and fifth S-fins; and

the second gate structure overlaps the top edge of α-type cell region.

15. The semiconductor device of claim 13 , wherein:

the α-type cell region is a first α-type cell region;

each of a third one of the rows (third row) and a fourth one of the rows (fourth row) having a single-row height relative to the second direction, top and bottom boundaries correspondingly of each of the first and second rows being aligned with corresponding ones of the tracks;

relative to the second direction, the third row and being stacked under the first row, and the fourth row being stacked under the first row;

a second alpha-type (α-type) cell region having first and second portions correspondingly in the fourth and third rows such that the second α-type cell region has the double-row height;

the second α-type cell region including fourth, fifth and sixth F-fins, fourth, fifth and sixth S-fins and a second gate structure;

a top edge of the second α-type cell region being co-track aligned with the top boundary of the third row and free from being overlapped by the fourth to sixth F-fins and the fourth to sixth S-fins;

a bottom edge of the second α-type cell region being co-track aligned correspondingly with the bottom boundary of the fourth row and being overlapped by the fifth S-fin;

the top boundary of the fourth row and the bottom boundary of the third row being co-track aligned and overlapped by the fifth F-fin; and

the second gate structure overlapping each of the fourth to sixth F-fins and the first to sixth S-fins, and being free from overlapping the top edge of the second α-type cell region.

16. The semiconductor device of claim 15 , wherein:

a fifth one of the rows (fifth row) has the single-row height, top and bottom boundaries of the second row being aligned with corresponding ones of the tracks;

relative to the second direction, the fifth row is stacked under the fourth row;

the fifth row includes a beta-type (β-type) cell region which has at least the single-row height;

relative to the first direction, the β-type cell region is aligned with the second α-type cell region;

the β-type cell region includes at least a seventh F-fin, at least a seventh S-fin and a third gate structure;

a top edge of the β-type cell region is co-track aligned with the bottom boundary of the third row and free from being overlapped by the seventh F-fin and the seventh S-fin;

the third gate structure overlaps the seventh F-fin and the seventh S-fin; and

the third gate structure is free from overlapping the fifth S-fin.

17. A method of fabricating a semiconductor device, the method comprising:

forming fins representing active regions, the fins extending in a first direction, the forming fins including:

arranging the fins to be aligned along tracks;

arranging the fins in rows,

a first one of the rows (first row) having a single-row height relative to a second direction perpendicular to the first direction, and

top and bottom boundaries of the first row being aligned with corresponding ones of the tracks;

configuring first, second and third ones of the fins to have a first conductivity type (first, second and third F-fins); and

configuring fourth, fifth and sixth ones of the fins to have a different second conductivity type (first, second and third S-fins);

forming gate structures extending in the second direction, the forming gate structures including:

forming a first one of the gate structures (first gate structure) to overlap each of the first F-fin and the first S-fin; and

forming a second one of the gate structures (second gate structure) to overlap each of the second F-fin and the second S-fin, the second gate structure further overlapping at least one of the third F-fin or the third S-fin; and

forming first-row components in the first row that represent cell regions, the forming first-row components including:

forming first ones of the first-row components that, in combination with the first F-fin, the first S-fin and the first gate structure, represent an alpha-type (α-type) cell region; and

forming second ones of the first-row components that, in combination with the second F-fin, the third F-fin, the second S-fin, the third S-fin and the second gate structure, represent a beta-type (β-type) cell region; and

wherein:

each of the α-type cell region and the β-type cell region having the single-row height;

top and bottom edges of the α-type cell region being co-track aligned correspondingly with the top and bottom boundaries of the first row and free from being overlapped by the first F-fin or the first S-fin;

the forming gate structures further including:

forming the first gate structure to be free from overlapping the top and bottom edges of the α-type cell region;

a top edge of the β-type cell region being co-track aligned with the top boundary of the first row and co-track aligned with the third F-fin; and

a bottom edge of the β-type cell region being co-track aligned with the bottom boundary of the first row and co-track aligned with the third S-fin.

18. The method of claim 17 , wherein: the a-type cell region is a first a-type cell region; the forming fins further includes: configuring a seventh one of the fins to have the first conductivity type (fourth F-fin); and configuring an eighth one of the fins to have the second conductivity type (fourth S-fin); the forming gate structures further includes: forming a third one of the gate structures (third gate structure) to overlap the fourth F-fin and the fourth S-fin; and the forming gate structures further includes: forming the second gate structure to overlap the third F-fin; and forming the third gate structure to be free from overlapping the third F-fin; a second one of the rows (second row) has the single-row height, top and bottom boundaries of the second row being aligned with corresponding ones of the tracks; relative to the second direction, the second row is stacked on the first row; the method further comprises: forming second-row components in the second row that represent cell regions, the forming second-row components including: forming first ones of the second-row components that, in combination with the fourth F-fin, the fourth S-fin and the third gate structure, represent a second a-type cell region which has the single-row height; relative to the first direction, the second a-type cell region is aligned with the j3-type cell region; and a bottom edge of the second a-type cell region is co-track aligned with the top boundary of the first row and free from being overlapped either of the fourth F-fin or the fourth S-fin.

19. The method of claim 18 , wherein the forming gate structures further includes:

forming the second gate structure to overlap the third S-fin.

20. The method of claim 18 , wherein the forming gate structures further includes:

forming the second gate structure to be free from overlapping the third S-fin.

Assignments (1)

Continuity (4)

References Cited (28)