N-channel and P-channel end-to-end finfet cell architecture

1. A data processing system adapted to process a computer implemented representation of a circuit design, comprising:

a data processor and memory coupled to the data processor, the memory storing instructions executable by the data processor, including instructions to match cells specified in a machine readable circuit description with cells in a cell library, the cell library including a plurality of cells having a base structure comprising:

a first block including a first set of semiconductor fins aligned in a first direction;

a second block including a second set of semiconductor fins aligned in the first direction;

an inter-block isolation structure in a third region having a first side adjacent to the first block and a second side adjacent to the second block, wherein semiconductor fins in the first set extend away from the inter-block isolation structure, have ends proximal to the first side of the inter-block isolation structure and have ends distal to the inter-block isolation structure, and wherein semiconductor fins in the second set extend away from the inter-block isolation structure, have ends proximal to the second side of the inter-block isolation structure and have ends distal to the inter-block isolation structure;

cells in the plurality of cells including:

a patterned gate conductor layer on the base structure including a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins;

a plurality of patterned conductor layers on the base structure, one or more conductive conductors in the plurality of patterned conductor layers being arranged to connect a semiconductor fin in the first set to a semiconductor fin in the second set, arranged to connect the first gate conductor to the second gate conductor, and arranged to connect a power conductor to at least one semiconductor fin in one of the first and second sets; and

a plurality of interlayer connectors on the base structure that connect semiconductor fins, gate conductors, and conductors in the plurality of patterned conductor layers.

2. The system of claim 1 , wherein semiconductor fins in the second set are aligned end-to-end with semiconductor fins in the first set.

3. The system of claim 1 , including:

at least one patterned conductor layer in the plurality of patterned conductor layers, including an inter-block conductor parallel, and adjacent to, one of the semiconductor fins in the first set and one of the semiconductor fins in the second set, the inter-block conductor connecting the first gate conductor to the second gate conductor.

4. The system of claim 1 , including:

at least one patterned conductor layer, including an inter-block conductor arranged to connect a first semiconductor fin in the first set to a second semiconductor fin in the second set, wherein the second semiconductor fin is aligned end-to-end with first semiconductor fin.

5. The system of claim 1 , wherein the first and second sets of fins include transistor channels, sources and drains, and including stressor structures on the sources and drains.

6. The system of claim 1 , wherein the end proximal to the first side of the inter-block isolation structure on at least one fin in the first set of semiconductor fins includes a stressor structure either on said end or between said end and the first gate conductor.

7. The system of claim 1 , wherein the end proximal to the first side of the inter-block isolation structure on at least one fin in the first set of semiconductor fins includes a first stressor structure either on said end or between said end and the first gate conductor; and the end proximal to the second side of the inter-block isolation structure on at least one fin in the second set of semiconductor fins includes a second stressor structure either on said end or between said end and the second gate conductor.

8. The system of claim 1 , including power connectors coupled with the first and second sets of semiconductor fins.

9. The system of claim 1 , wherein the semiconductor fins in the first and second sets have widths less than 20 nm.

10. The system of claim 1 , wherein the members of the first set of semiconductor fins are configured for formation of a single finFET, with a first source/drain region adjacent to the inter-block isolation structure and a second source/drain region, and include first uniform structures including their first source/drain region and second uniform structures including their second source/drain regions.

11. The system of claim 10 , wherein the members of the second set of semiconductor fins are configured for formation of a single finFET, with a first source/drain region adjacent to the inter-block isolation structure and a second source/drain region, and include third uniform structures including their first source/drain region and fourth uniform structures including their second source/drain regions.

12. The system of claim 11 , wherein the first, second, third and fourth uniform structures include stressors.

13. The system of claim 1 , wherein the members of the first set of semiconductor fins are configured for formation of multiple finFETs each.