Circuits and methods for self-adaptive decision-feedback equalization in a memory system
Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.
1. A signal receiver to sample a plurality of digital signals conveyed in parallel from a memory controller and timed to a timing-reference signal from the memory controller, the signal receiver comprising:
a plurality of decision-feedback equalizers, each decision-feedback equalizer including:
a sampler having a sampler input port to receive a respective one of the plurality of digital signals conveyed in parallel from the memory controller;
a tap port to receive a respective equalizer-tap value; and
a timing port to receive the timing-reference signal from the memory controller;
each decision-feedback equalizer to equalize the respective digital signal on the sampler input port responsive to the respective equalizer-tap value; and
an adaptive tap-value generator coupled to the tap port of one of the decision-feedback equalizers, the adaptive tap-value generator including a monitor sampler, to produce monitor samples of the digital signal to the one of the decision-feedback equalizers, and to generate the respective equalizer-tap value for the one of the decision-feedback equalizers as a function of least-mean squares of errors at the sampler input port of the one of the decision-feedback equalizers;
wherein the digital signals are binary signals, the adaptive tap-value generator generating the equalizer-tap values for the one of the decision-feedback equalizers as a function of the errors for only one of two levels of the digital signal.
2. The signal receiver of claim 1 , wherein the digital signals conveyed in parallel from the memory controller represent data for storage in a memory.
3. The signal receiver of claim 1 , wherein the digital signals conveyed in parallel from the memory controller comprise at least one of command signals and address signals.
4. The signal receiver of claim 1 , wherein the adaptive tap-value generator is coupled to the tap port of more than one of the decision-feedback equalizers.
5. The signal receiver of claim 1 , further comprising a plurality of analog front ends, one for each of the plurality of decision-feedback equalizers, for equalizing the respective digital signals to the decision-feedback equalizers.
6. The signal receiver of claim 1 , wherein the timing-reference signal comprises a strobe signal.
7. An integrated circuit for receiving digital signals conveyed in parallel from a memory controller and timed to a timing-reference signal from the memory controller, the integrated circuit comprising:
a plurality of decision-feedback equalizers, each decision-feedback equalizer including a sampler having a sampler input port to receive a respective one of the plurality of digital signals conveyed in parallel from the memory controller, a tap port to receive a respective equalizer-tap value, and a timing port to receive the timing-reference signal from the memory controller, each decision-feedback equalizer to equalize the respective digital signal responsive to the respective equalizer-tap value; and
an adaptive tap-value generator coupled to the tap port of one of the decision-feedback equalizers, the adaptive tap-value generator including a monitor sampler, to produce monitor samples of the digital signal to the one of the decision-feedback equalizers, and to generate the respective equalizer-tap value for the one of the decision-feedback equalizers as a function of least-mean squares of errors to the sampler input port of the decision-feedback equalizer;
wherein the digital signals are binary signals, the adaptive tap-value generator generating the equalizer-tap values for the one of the decision-feedback equalizers as a function of the least-mean square of error for only one of two levels of the digital signal to the one of the decision-feedback equalizer.
8. The integrated circuit of claim 7 , wherein the digital signals conveyed in parallel from the memory controller represent data for storage, the integrated circuit further comprising an array of memory cells to store the data.
9. The integrated circuit of claim 8 , further comprising an output port to convey the equalized digital signals from the integrated circuit.
10. The integrated circuit of claim 9 , wherein the output port connects the integrated circuit to a control interface of a memory component.
11. The integrated circuit of claim 9 , wherein the output port connects the integrated circuit to a data interface of a memory component.
12. The integrated circuit of claim 7 , wherein the adaptive tap-value generator is coupled to the tap port of more than one of the decision-feedback equalizers.
13. The integrated circuit of claim 7 , further comprising a plurality of analog front ends, one for each of the plurality of decision-feedback equalizers, for equalizing the respective digital signals to the decision-feedback equalizers.
14. The integrated circuit of claim 7 , wherein the timing-reference signal comprises a strobe signal.
15. A memory module comprising:
a module connector to receive data signals, a data-timing signal, address signals, and an address-timing signal from a memory controller;
a data-buffer component coupled to the module connector to receive the data signals and the data-timing signal, the data-buffer component including:
a plurality of decision-feedback equalizers, each decision-feedback equalizer including a sampler having a sampler input port to receive a respective one of the data signals conveyed in parallel from the memory controller, a tap port to receive a respective equalizer-tap value, and a timing port to receive the data-timing signal from the memory controller, each decision-feedback equalizer to equalize the respective data signal responsive to the respective equalizer-tap value; and
an adaptive tap-value generator coupled to the tap port of one of the decision-feedback equalizers, the adaptive tap-value generator including a monitor sampler, to produce monitor samples of the data signal to the one of the decision-feedback equalizers, and to generate the respective equalizer-tap value for the one of the decision-feedback equalizers as a function of least-mean squares of errors to the sampler input port of the decision-feedback equalizer;
an address-buffer component coupled to the module connector to receive the address signals and the address-timing signal from the memory controller, the address-buffer component including an address-output port to relay the address signals; and
a memory component having an array of memory cells, a memory-component data port coupled to the decision-feedback equalizers to receive the equalized data signals, and a memory-component address port coupled to the address-buffer component to receive the relayed address signals.
16. The memory module of claim 15 , the address-buffer component further including a second plurality of decision-feedback equalizers to equalize the address signals received from the memory controller.
17. The memory module of claim 16 , the address-buffer component further including a second adaptive tap-value generator coupled to at least one of the second plurality of decision-feedback equalizers, the second adaptive tap-value generator to generate a second equalizer-tap value as a function of least-mean squares of the errors.
18. The memory module of claim 15 , wherein the data-timing signal comprises a strobe signal, the address-timing signal comprises a clock signal that oscillates during times when the strobe signal is inactive.