Methods and circuits for asymmetric distribution of channel equalization between devices
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
1. A memory system comprising:
a memory controller;
a memory integrated-circuit; and
a memory buffer communicatively disposed between the memory controller and the memory integrated-circuit, the memory buffer including:
a transmit equalizer having a transmit-data input node to receive a transmit signal and a transmit-equalizer control port to receive a transmit coefficient, the transmit equalizer to produce an equalized signal responsive to the transmit signal and the transmit coefficient;
a receive port coupled to the memory integrated-circuit to receive, from the memory integrated-circuit, a corrupted signal that includes inter-symbol interference;
a signal monitor coupled to the receive port to receive the corrupted signal and to provide a measure of the inter-symbol interference of the corrupted signal; and
equalization control circuitry coupled between the signal monitor and the transmit-equalizer control port, the equalization control circuity to derive the transmit coefficient from the measure of the inter-symbol interference.
2. The memory system of claim 1 , the memory buffer further comprising a receive equalizer having a receive-equalizer control port, the receive equalizer to equalize the inter-symbol interference of the corrupted signal to produce a second equalized signal.
3. The memory system of claim 2 , the memory buffer to buffer the second equalized signal to the memory controller.
4. The memory system of claim 2 , wherein the equalization control circuitry is coupled to the receive-equalizer control port.
5. The memory system of claim 2 , wherein the signal monitor is coupled to the receive port via the receive equalizer.
6. The memory system of claim 1 , wherein the transmit equalizer includes a pre-cursor filter tap, and wherein the equalization control circuitry controls the pre-cursor filter tap based upon the measure of the inter-symbol interference of the corrupted signal.
7. The memory system of claim 1 , the memory buffer further including:
a second transmit equalizer having a second transmit-data input node to receive a second transmit signal and a second transmit-equalizer control port to receive a second transmit coefficient, the second transmit equalizer to produce a second equalized signal responsive to the second transmit signal and the second transmit coefficient;
a second receive port coupled to the memory controller to receive, from the memory controller, a second corrupted signal that includes second inter-symbol interference;
a second signal monitor coupled to the second receive port to receive the second corrupted signal and to provide a second measure of the second inter-symbol interference of the second corrupted signal; and
second equalization control circuitry coupled between the second signal monitor and the second transmit-equalizer control port, the second equalization control circuity to derive the second transmit coefficient from the second measure of the second inter-symbol interference.
8. The memory system of claim 1 , further comprising at least one additional memory integrated-circuit coupled to the memory buffer.
9. The memory system of claim 8 , further comprising a multi-drop bus connecting the memory integrated-circuit and the at least one additional memory integrated-circuit to the memory buffer.
10. The memory system of claim 1 , the memory buffer further comprising a receive equalizer to equalize the corrupted signal responsive to a pre-cursor receive coefficient.
11. The memory system of claim 10 , the equalization control circuitry including a calibration block to calculate the pre-cursor receive coefficient.
12. The memory system of claim 11 , wherein the transmit coefficient is a pre-cursor transmit coefficient.
13. A method of buffering signals between a memory controller and an integrated-circuit memory device, the method comprising:
receiving data from the memory controller;
producing, from the data, a transmit signal;
equalizing the transmit signal responsive to a transmit coefficient;
transmitting the equalized transmit signal to the integrated-circuit memory device;
receiving a corrupted signal from the integrated-circuit memory device, the corrupted signal expressing a series of symbols and including inter-symbol interference;
measuring the inter-symbol interference; and
updating the transmit coefficient responsive to the inter-symbol interference.
14. The method of claim 13 , further comprising equalizing the corrupted signal responsive to a receive coefficient.
15. The method of claim 14 , further comprising updating the receive coefficient responsive to the inter-symbol interference.
16. The method of claim 15 , wherein the receive coefficient is a pre-cursor coefficient.
17. The method of claim 14 , further comprising sampling the corrupted signal after the equalizing of the corrupted signal and transmitting the sampled corrupted signal to the memory controller.
18. The method of claim 13 , wherein the receiving the data from the memory controller comprises receiving a second corrupted signal expressing the data and including second inter-symbol interference, the method further comprising deriving a receive coefficient from the second inter-symbol interference and equalizing the second corrupted signal responsive to the receive coefficient.
19. The method of claim 18 , further comprising deriving a second transmit coefficient from the second inter-symbol interference and transmitting a second signal, expressing the series of symbols and equalized responsive to the transmit coefficient, to the memory controller.