IP Library Granted Patent US 12,538,812
Granted Patent B2
US 12,538,812 · App. 18/165,545 · Granted Jan 27, 2026

Semiconductor packages with wettable flanks and related methods

Inventors: Hui Min Ler (Seremban, MY); Swee Har Khor (Kuala Lumpur, MY); Ziming Chang (Tampin, MY); Kok Yang Lau (Asahan, MY); Heng Giap Ong (Seremban, MY)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/49582H01L21/561H01L24/96H01L2224/95001H01L2224/96
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Quick Facts
Patent No.
US 12,538,812
App. No.
18/165,545
Granted
Jan 27, 2026
Kind
B2
Abstract

Implementations of a method of providing wettable flanks on leads of a semiconductor package may include applying mold compound around a plurality of leads included in a leadframe; electroplating exposed portions of the plurality of leads; cutting at least one lead of the plurality of leads to expose a flank of the least one lead; applying an electrically conductive layer over the plurality of leads; electroplating the flank of the at least one lead to render the flank wettable; removing the electrically conductive layer from the plurality of leads; and singulating to form a semiconductor package.

Claims (41)

1 . A method of providing wettable flanks on leads of a semiconductor package, the method comprising:

applying mold compound around a plurality of leads comprised in a leadframe;

electroplating exposed portions of the plurality of leads;

cutting at least one lead of the plurality of leads to expose a flank of the least one lead;

applying an electrically conductive layer over the plurality of leads;

electroplating the flank of the at least one lead to render the flank wettable;

removing the electrically conductive layer from the plurality of leads; and

singulating the leadframe, after removing the electrically conductive layer, to form a semiconductor package.

2 . The method of claim 1 , wherein the electrically conductive layer is an electrically conductive tape.

3 . The method of claim 2 , wherein the electrically conductive tape covers the entire leadframe.

4 . The method of claim 2 , wherein the electrically conductive tape covers only a portion of a single side of the semiconductor package.

5 . The method of claim 1 , wherein an electroplated die flag of the leadframe is exposed when the electrically conductive layer is coupled over the at least one lead.

6 . The method of claim 1 , wherein electroplating the flank of the at least one lead further comprises rendering the flank wettable by reaching a plating thickness greater than 2 microns.

7 . A method of providing wettable flanks on leads of a plurality of semiconductor packages, the method comprising:

applying mold compound around a plurality of leads comprised in a semiconductor package, the semiconductor package one of a plurality of semiconductor packages comprised in a leadframe panel;

electroplating exposed portions of the plurality of leads;

cutting at least one lead of the plurality of leads to expose a flank of the least one lead;

applying an electrically conductive layer over the plurality of leads;

electroplating the flank of the at least one lead to render the flank wettable;

removing the electrically conductive layer; and

singulating the leadframe panel after removing the electrically conductive layer to form the plurality of semiconductor packages.

8 . The method of claim 7 , wherein the electrically conductive layer is an electrically conductive tape.

9 . The method of claim 8 , wherein the electrically conductive tape covers the entire leadframe panel.

10 . The method of claim 8 , wherein the electrically conductive tape covers only a portion of a single side of each semiconductor package.

11 . The method of claim 7 , wherein the electrically conductive layer electrically couples the at least one lead with the leadframe panel.

12 . The method of claim 7 , wherein electroplating the flank of the at least one lead further comprises rendering the flank wettable by reaching a plating thickness greater than 2 microns.

13 . The method of claim 7 , wherein an electroplated die flag of the leadframe panel is exposed when the electrically conductive layer is coupled over the at least one lead.

14 . A method of providing wettable flanks on leads of a plurality of semiconductor packages, the method comprising:

applying mold compound around a plurality of leads comprised in a semiconductor package, the semiconductor package one of a plurality of semiconductor packages comprised in a leadframe panel;

electroplating exposed portions of the plurality of leads;

cutting at least one lead of the plurality of leads to form a plurality of cut leads each comprising a flank;

coupling a jig over the plurality of leads, the jig providing an electrical connection to each of the plurality of cut leads using a pogo pin;

electroplating the plurality of cut leads to render the flank of each cut lead wettable;

removing the jig from the plurality of leads; and

singulating the leadframe panel to form the plurality of semiconductor packages.

15 . The method of claim 14 , wherein the jig is sized to contact each cut lead of the plurality of cut leads in the leadframe panel.

16 . The method of claim 14 , wherein the jig comprises electrically nonconductive material that forms a frame around each semiconductor package of the leadframe panel.

17 . The method of claim 16 , wherein electrically nonconductive material comprises electrical routing that electrically couples each cut lead of the plurality of cut leads together.

18 . The method of claim 14 , wherein electroplating the plurality of cut leads to render the flank of each cut lead wettable further comprises rendering the flank wettable by reaching a plating thickness greater than 2 microns.

19 . The method of claim 4 , wherein the pogo pin is spring loaded to apply a bias force to the cut lead.

20 . The method of claim 14 , wherein the jig comprises a plurality of windows therethrough, each window sized to correspond with a size of each semiconductor package of the leadframe panel and wherein one or more pogo pins are supported within each window at one or more locations corresponding with one or more cut leads.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 064502, FRAME 0293 Recorded Nov 14, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 065566/0488 →
SECURITY INTEREST Recorded May 9, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 065402/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2023
From: LER, HUI MIN; KHOR, SWEE HAR; CHANG, ZIMING; LAU, KOK YANG; ONG, HENG GIAP
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 062614/0674 →