Semiconductor device including source/drain contact having height below gate stack

1. A method, comprising:

arranging a first gate structure extending continuously above a first active region and a second active region of a substrate;

arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and

arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

2. The method of claim 1 , further comprising:

arranging a second separation spacer disposed on a second gate structure to isolate an electronic signal transmitted through a third gate via and a fourth gate via that are disposed on the second gate structure.

3. The method of claim 2 , wherein the first to fourth gate via are disposed outside a non-active region arranged between the first active region and the second active region.

4. The method of claim 1 , further comprising:

arranging a second local interconnect over a non-active region between the first active region and the second active region, to couple a third contact arranged above the first active region to a fourth contact arranged above the second active region.

5. The method of claim 1 , further comprising:

arranging a second gate structure extending continuously above the first active region and the second active region;

arranging a third gate via and a fourth gate via that are disposed on the second gate structure; and

when a guideline is followed, arranging the first local interconnect adjacent to the first gate structure or the second gate structure, wherein the guideline indicates that the first gate via and the second gate via are coupled with the first gate structure, the third gate via and the fourth gate via are coupled with the second gate structure, at least one of the first to fourth gate via is arranged above the first active region or the second active region, and a first pitch between the first gate via and the second gate via is substantially equal to a second pitch between the third gate via and the fourth gate via.

6. The method of claim 1 , wherein the first separation spacer overlaps the first local interconnect.

7. The method of claim 1 , wherein the first separation spacer overlaps a non-active region connecting the first active region and the second active region, without overlapping the first active region and the second active region.

8. The method of claim 1 , further comprising:

when a guideline indicates that at least one of the first contact and the second contact above the first active region and the second active region is an output drain of a standard cell, arranging no local interconnect around the output drain.

9. The method of claim 1 , further comprising:

arranging a second gate structure extending continuously above the first active region and the second active region; and

arranging a third gate via and a fourth gate via that are disposed on the second gate structure.

10. A method, comprising:

arranging a plurality of gate structures above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure, wherein the first and second active regions are spaced apart by the non-active region;

arranging a plurality of contacts above the first and second active regions;

arranging a first separation spacer between the plurality of contacts;

arranging at least one first gate via above the first active region or the second active region, wherein the at least one first gate via is electrically coupled with at least one of the plurality of gate structures; and

selectively arranging at least one local interconnect over the non-active region, to couple a first contact of the plurality of contacts above the first active region to a second contact of the plurality of contacts above the second active region.

11. The method of claim 10 , further comprising:

arranging a second separation spacer between the plurality of contacts, wherein the first and second separation spacers overlap the non-active region.

12. The method of claim 11 , wherein the first and second separation spacers are separated from each other by the at least one local interconnect.

13. The method of claim 10 , wherein the at least one first gate via comprises a first via and a second via,

wherein arranging the at least one first gate via further comprises:

arranging the first and second vias that are staggered along a first direction in which the first active region extends.

14. The method of claim 13 , wherein arranging the plurality of contacts further comprises:

staggering one or more contacts of the plurality of contacts along the first direction, wherein the one or more contacts of the plurality of contacts are separated from each other by the plurality of gate structures extending in a second direction different from the first direction.

15. The method of claim 10 , further comprising:

arranging a second gate via above the second active region when the at least one first gate via is above the first active region, wherein the first separation spacer is between the at least one first gate via and the second gate via.

16. A method, comprising:

arranging a first gate structure extending continuously above a first active region and a second active region of a substrate;

arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure; and

arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed above the first active region and a second contact disposed above the second active region,

wherein the first separation spacer overlaps the first local interconnect and has a width larger than a width of the first gate structure.

17. The method of claim 16 , further comprising:

arranging a second gate structure extending continuously above the first active region and the second active region; and

arranging a second separation spacer disposed on the second gate structure to electrically isolate a third gate via from a fourth gate via that are disposed on the second gate structure.

18. The method of claim 17 , wherein a width of the second separation spacer is larger than a width of the second gate structure.

19. The method of claim 17 , wherein a distance between the third gate via and the second separation spacer is different from a distance between the fourth gate via and the second separation spacer.

20. The method of claim 16 , further comprising:

arranging a second local interconnect that is next to the first gate structure and overlapped by the first separation spacer, wherein the second local interconnect is electrically coupled to a third contact disposed above the first active region and a fourth contact disposed above the second active region.