Error processing circuit, memory and operation method of the memory

1. An error processing circuit comprising:

a first H matrix calculation circuit configured to calculate a first H matrix and upstream data to generate a partial first parity, during an encoding operation;

a second H matrix calculation circuit configured to calculate a second H matrix and the upstream data to generate a second parity, during the encoding operation;

a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the encoding operation; and

a correction circuit configured to, based on syndromes calculated using the first H matrix and the second H matrix, correct errors in read data read from a memory,

wherein the error processing circuit outputs error corrected data.

2. The error processing circuit of claim 1 , wherein:

the first H matrix calculation circuit is further configured to calculate the first H matrix and downstream data to generate a partial first downstream parity, during a decoding operation, and

the second H matrix calculation circuit is further configured to calculate the second H matrix and the downstream data to generate a second downstream parity, during the decoding operation.

3. The error processing circuit of claim 2 , further comprising:

a parity restoration circuit configured to sum the first parity transferred for a decoding operation and the second parity transferred for the decoding operation to generate a restored partial first parity, during the decoding operation;

a first syndrome calculation circuit configured to sum the restored partial first parity and the partial first downstream parity to generate a first syndrome, during the decoding operation; and

a second syndrome calculation circuit configured to sum the second parity transferred for the decoding operation and the second downstream parity to generate a second syndrome, during the decoding operation,

wherein the correction circuit is configured to correct an error of the downstream data based on the first syndrome and the second syndrome.

4. The error processing circuit of claim 3 , wherein the correction circuit determines that there is no error in the downstream data, when values of the first syndrome and the second syndrome are all ‘0’.

5. The error processing circuit of claim 3 , wherein the correction circuit corrects the error by inverting bits corresponding to the values of the first syndrome and the second syndrome among multiple bits of the downstream data.

6. The error processing circuit of claim 1 ,

wherein the upstream data are of N bits, where N is an integer equal to or greater than 2, the first parity is of M bits, where M is an integer equal to or greater than 2, and the first H matrix is a (M×N) matrix, and

wherein the first H matrix calculation circuit generates the partial first parity by calculating matrix multiplication of the first H matrix and the upstream data expressed as a (N×1) matrix.

7. The error processing circuit of claim 6 ,

wherein the second parity is of K bits, where K is an integer equal to or greater than 2, and the second H matrix is a (K×N) matrix, and

wherein the second H matrix calculation circuit generates the second parity by calculating matrix multiplication of the second H matrix and the upstream data expressed as the (N×1) matrix.

8. An error processing circuit comprising:

a first H matrix calculation circuit configured to calculate a first H matrix and downstream data to generate a partial first downstream parity, during a decoding operation;

a second H matrix calculation circuit configured to calculate a second H matrix and the downstream data to generate a second downstream parity, during the decoding operation;

a parity restoration circuit configured to sum a first parity and a second parity to generate a restored partial first parity, during the decoding operation;

a first syndrome calculation circuit configured to sum the restored partial first parity and the partial first downstream parity to generate a first syndrome, during the decoding operation;

a second syndrome calculation circuit configured to sum the second parity and the second downstream parity for the decoding operation to generate a second syndrome, during the decoding operation; and

a correction circuit configured to correct an error of the downstream data based on the first syndrome and the second syndrome,

wherein the correction circuit outputs error corrected data.

9. The error processing circuit of claim 8 , wherein the correction circuit determines that there is no error in the downstream data, when values of the first syndrome and the second syndrome are all ‘0’.

10. The error processing circuit of claim 8 , wherein the correction circuit corrects the error by inverting bits corresponding to the values of the first syndrome and the second syndrome among multiple bits of the downstream data.

11. A memory comprising:

a first H matrix calculation circuit configured to calculate a first H matrix and write data to generate a partial first parity, during a write operation;

a second H matrix calculation circuit configured to calculate a second H matrix and the write data to generate a second parity, during the write operation;

a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the write operation;

a memory core configured to store the write data, the first parity, and the second parity during the write operation; and

a correction circuit is configured, based on syndromes calculated from the first H matrix and the second H matrix, to correct errors from read data read from the memory core,

wherein the correction circuit outputs error corrected read data.

12. The memory of claim 11 , wherein:

the first H matrix calculation circuit is further configured to calculate the first H matrix and read data read from the memory core to generate a partial first downstream parity, during a read operation, and

the second H matrix calculation circuit is further configured to generate, during the decoding operation, a second read parity by calculating the second H matrix and the read data.

13. The memory of claim 12 , further comprising:

a parity restoration circuit configured to sum the first parity and the second parity that are read from the memory core to generate a restored partial first parity, during the read operation;

a first syndrome calculation circuit configured to sum the restored partial first parity and the partial first read parity to generate a first syndrome, during the read operation;

a second syndrome calculation circuit configured to sum the second read parity and the second parity to generate a second syndrome, during the read operation,

wherein the correction circuit is configured to correct an error of the read data based on the first syndrome and the second syndrome.

14. The memory of claim 13 , wherein the correction circuit determines that there is no error in the read data, when values of the first syndrome and the second syndrome are all ‘0’.

15. The memory of claim 13 , wherein the correction circuit corrects the error by inverting bits corresponding to the values of the first syndrome and the second syndrome among multiple bits of the read data.

16. The memory of claim 12 ,

wherein the write data are of N bits, where N is an integer equal to or greater than 2, the first parity is of M bits, where M is an integer equal to or greater than 2, and the first H matrix is a (M×N) matrix, and

wherein the first H matrix calculation circuit generates the partial first parity by calculating matrix multiplication of the first H matrix and the write data expressed as a (N×1) matrix.

17. The memory of claim 16 ,

wherein the second parity is of K bits, where K is an integer equal to or greater than 2, and the second H matrix is a (K×N) matrix, and

wherein the second H matrix calculation circuit generates the second parity by calculating matrix multiplication of the second H matrix and the write data expressed as the (N×1) matrix.

18. A method for operating a memory, the method comprising:

receiving write data;

calculating matrix multiplication of a first H matrix and the write data to generate a partial first parity;

calculating matrix multiplication of a second H matrix and the write data to generate a second parity;

summing the partial first write parity and the second parity to generating a first parity;

storing the write data, the first parity, and the second parity in a memory core;

correcting errors in read data read from the memory based on syndromes calculated from the first H matrix and the second H matrix; and

outputting error corrected read data.

19. The method of claim 18 , further comprising:

reading read data and first and second parities that correspond to the read data from the memory core;

calculating matrix multiplication of the first H matrix and the read data to generate a partial first read parity;

calculating matrix multiplication of the second H matrix and the read data to generate a second read parity;

summing the first and second parities that correspond to the read data to generate a restored partial first parity;

summing the restored partial first parity and the partial first read parity to generate a first syndrome;

summing the second parity corresponding to the read data and the second read parity to generate a second syndrome;

correcting an error of the read data based on the first syndrome and the second syndrome; and

outputting the error-corrected read data.