IP Library Granted Patent US 12,048,255
Granted Patent B2
US 12,048,255 · App. 18/172,710 · Granted Jul 23, 2024

Hard mask and preparation method thereof, preparation method of josephson junction, and superconducting circuit

Inventors: Ran Gao (Hangzhou, CN); Jingwei Zhou (Hangzhou, CN); Chunqing Deng (Hangzhou, CN)
Assignee: Alibaba Group Holding Limited
H10N60/12H01L21/30608H10N60/0912H10N60/805H10N69/00
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Quick Facts
Patent No.
US 12,048,255
App. No.
18/172,710
Granted
Jul 23, 2024
Kind
B2
Abstract

A hard mask includes a silicon oxide layer provided on a bare silicon wafer; and a silicon nitride layer provided on the silicon oxide layer, wherein the silicon nitride is provided with a first pattern, the silicon oxide layer is provided with a second pattern corresponding to the first pattern, the first pattern and the second pattern have different shapes, and the first pattern and the second pattern are configured to assist in forming a Josephson junction on the bare silicon wafer.

Claims (30)

1. A method for preparing a hard mask, the method comprising:

forming a silicon oxide layer on a preset bare silicon wafer;

forming a silicon nitride layer on the silicon oxide layer; and

forming a first pattern on the silicon nitride layer and a second pattern corresponding to the first pattern on the silicon oxide layer to form a hard mask, wherein

the first pattern and the second pattern have different shapes,

the first pattern and the second pattern are formed in different directions; and

the first pattern and the second pattern are configured to assist in forming a Josephson junction on the bare silicon wafer.

2. The method of claim 1 , further comprising:

acquiring a stress of the silicon nitride layer; and

when the stress is greater than a preset stress threshold, adjusting a ratio between a nitrogen material and a silicon material in the silicon nitride layer to cause the stress to be smaller than or equal to the preset stress threshold.

3. The method of claim 1 , wherein forming the first pattern on the silicon nitride layer comprises:

forming an image transmission layer on the silicon nitride layer;

forming a third pattern on the image transmission layer; and

forming the first pattern on the silicon nitride layer based on the third pattern.

4. The method of claim 3 , wherein forming the third pattern on the image transmission layer comprises:

forming a photoresist layer on the image transmission layer;

forming a pattern to be transmitted on the photoresist layer; and

forming the third pattern on the image transmission layer based on the pattern to be transmitted.

5. The method of claim 3 , wherein forming the image transmission layer comprises forming the image transmission layer by a chromium material.

6. A method for preparing a Josephson junction, the method comprising:

forming a preset material on a preset bare silicon wafer through a first hard mask to generate a first structure;

forming the preset material on the preset bare silicon wafer through a second hard mask to generate a second structure, the first structure and the second structure being in different directions; and

generating the Josephson junction through the first structure and the second structure, the Josephson junction serving as a nonlinear inductance element.

7. The method of claim 6 , wherein the preset material comprises an aluminum material, a binary nitride material, a ternary nitride material, or a composite oxide material.

8. The method of claim 6 , wherein generating the Josephson junction through

the first structure and the second structure comprises:

acquiring an overlapping structure formed between the first structure and the second structure; and

determining the overlapping structure as the Josephson junction.

9. The method of claim 6 , wherein a direction of the first structure is perpendicular to a direction of the second structure.

10. The method of claim 6 , further comprising removing the first hard mask and the second hard mask.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2026
From: ALIBABA GROUP HOLDING LIMITED
To: Z-AXIS PTE. LTD.
Reel/Frame 075934/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2023
From: GAO, RAN; ZHOU, JINGWEI; DENG, CHUNQING
To: ALIBABA GROUP HOLDING LIMITED
Reel/Frame 062770/0485 →
Priority Claims (1)
CN 202010250679.5 · Apr 1, 2020 · national
Continuity (2)
Division 17216179 · Mar 29, 2021
Related Publication 20230210020A1 · Jun 29, 2023