IP Library Granted Patent US 11,804,533
Granted Patent B2
US 11,804,533 · App. 18/173,541 · Granted Oct 31, 2023

Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers

Inventors: Walter A. Harrison (Palo Alto, CA); Paul A. Clifton (Palo Alto, CA); Andreas Goebel (Palo Alto, CA); R. Stockton Gaines (Santa Monica, CA)
Assignee: Acorn Semi, LLC
H01L29/47H01L21/283H01L21/28512H01L21/28518H01L21/324H01L29/045H01L29/161H01L29/456
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Quick Facts
Patent No.
US 11,804,533
App. No.
18/173,541
Granted
Oct 31, 2023
Kind
B2
Abstract

Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Claims (10)

1. A method of forming an electrical contact, comprising:

forming, by segregation, an ordered monolayer of atoms out of a layer of material that is in contact with a surface of a semiconductor, wherein those atoms segregated as the monolayer are initially introduced into the layer of material, and thereafter, are segregated through annealing so as to form the ordered monolayer coordinated with and bonded to atoms at the surface of the semiconductor; and

depositing a barrier metal to form an electrical contact to the semiconductor with the ordered monolayer of atoms interposed therebetween, enabling an electrical current to pass between the barrier metal and the semiconductor through the ordered monolayer of atoms when the electrical contact is electrically biased.

2. The method of claim 1 , wherein the layer of material is a doped silicon oxide layer or silicon nitride layer, and following the annealing, performing a wet chemical etching leaving behind the ordered monolayer of atoms in contact with the surface of the semiconductor.

3. The method of claim 1 , wherein the barrier metal comprises tantalum nitride, titanium nitride, or ruthenium.

4. The method of claim 2 , wherein the barrier metal comprises tantalum nitride, titanium nitride, or ruthenium.

5. The method of claim 1 , wherein the ordered monolayer of atoms is an ordered monolayer of group V atoms.

6. The method of claim 1 , wherein the ordered monolayer of atoms is an ordered monolayer of group III atoms.

7. The method of claim 2 , wherein the ordered monolayer of atoms is an ordered monolayer of group V atoms.

8. The method of claim 2 , wherein the ordered monolayer of atoms is an ordered monolayer of group III atoms.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2023
From: HARRISON, WALTER A.; CLIFTON, PAUL A.; GOEBEL, ANDREAS; GAINES, R. STOCKTON
To: ACORN TECHNOLOGIES, INC.
Reel/Frame 062787/0367 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2023
From: ACORN TECHNOLOGIES, INC.
To: ACORN SEMI, LLC
Reel/Frame 062787/0414 →
Continuity (7)
Continuation 17247803 · Dec 23, 2020
Continuation 16706510 · Dec 6, 2019
Continuation 15684707 · Aug 23, 2017
Continuation 15146562 · May 4, 2016
Continuation 14360473
Provisional Application 61563478 · Nov 23, 2011
Related Publication 20230207657A1 · Jun 29, 2023