Storage wafer and manufacturing method of storage wafer
A storage wafer includes: a first semiconductor; a first element layer provided on the first semiconductor; a first pad provided on a first region of the first element layer; a second pad provided on a second region of the first element layer; an adhesive film provided on the second region; a second semiconductor provided on the adhesive film; a second element layer provided on the second semiconductor; and a third pad provided on the second element layer. The first element layer includes: first and second memory chip units coupled to the first and second pads, respectively. The second element layer includes an element coupled to the third pad and isolated from both the first and second pad.
1 . A storage wafer comprising:
a first semiconductor;
a first element layer provided on an upper surface of the first semiconductor;
a first pad provided on an upper surface of a first region of the first element layer;
a second pad provided on an upper surface of a second region different from the first region of the first element layer;
an adhesive film provided on the upper surface of the second region of the first element layer including the second pad;
a second semiconductor provided on an upper surface of the adhesive film;
a second element layer provided on an upper surface of the second semiconductor; and
a third pad provided on an upper surface of the second element layer,
wherein
the first element layer includes:
a first memory chip unit electrically coupled to the first pad; and
a second memory chip unit electrically coupled to the second pad,
the second element layer includes an element electrically coupled to the third pad and electrically isolated from both the first pad and the second pad, and
the second pad is electrically isolated from an external electrode by the adhesive film, the external electrode being provided on an outside of the storage wafer.
2 . The storage wafer according to claim 1 , wherein
the element includes a third memory chip unit.
3 . The storage wafer according to claim 2 , wherein
a memory capacity of the second memory chip unit is smaller than a memory capacity of the first memory chip unit and a memory capacity of the third memory chip unit.
4 . The storage wafer according to claim 1 , wherein
the element has a function different from functions of the first memory chip unit and the second memory chip unit.
5 . The storage wafer according to claim 4 , wherein
a position of the element is independent on a memory capacity of the second memory chip unit.
6 . The storage wafer according to claim 1 , further comprising:
an insulating layer provided on upper surfaces of the first element layer and the second element layer;
a first conductive layer which is in contact with the first pad in the insulating layer;
a fourth pad including a lower surface which is in contact with an upper surface of the first conductive layer and an upper surface which is not in contact with the insulating layer;
a second conductive layer which is in contact with the third pad in the insulating layer; and
a fifth pad including a lower surface which is in contact with an upper surface of the second conductive layer and an upper surface which is not in contact with the insulating layer.
7 . The storage wafer according to claim 1 , further comprising:
an insulating layer provided on upper surfaces of the first element layer and the second element layer;
a first conductive layer which is in contact with the first pad in the insulating layer;
a second conductive layer which is in contact with the third pad in the insulating layer;
a third conductive layer which is in contact with the first conductive layer and the second conductive layer; and
a sixth pad including a lower surface which is in contact with an upper surface of the third conductive layer and an upper surface which is not in contact with the insulating layer.
8 . The storage wafer according to claim 1 , wherein
a memory chip unit provided in the second region of the first element layer is a memory chip unit determined as being defective.
9 . A storage wafer comprising:
a first semiconductor including a first region and a second region whose upper surface is lower than the first region;
a first element layer provided on an upper surface of the first region of the first semiconductor;
a first pad provided on an upper surface of the first element layer;
an adhesive film provided on an upper surface of the second region of the first semiconductor;
a second semiconductor provided on an upper surface of the adhesive film;
a second element layer provided on an upper surface of the second semiconductor; and
a second pad provided on an upper surface of the second element layer,
wherein
the first element layer includes a first memory chip unit electrically coupled to the first pad;
the second element layer includes an element electrically coupled to the second pad and electrically isolated from the first pad, and
the first pad and the second pad are provided in substantially a same plane.
10 . The storage wafer according to claim 9 , wherein
the element includes a second memory chip unit.
11 . The storage wafer according to claim 9 , wherein
the element has a function different from that of the first memory chip unit.
12 . The storage wafer according to claim 9 , further comprising:
an insulating layer provided on upper surfaces of the first element layer and the second element layer;
a first conductive layer which is in contact with the first pad in the insulating layer;
a third pad including a lower surface which is in contact with an upper surface of the first conductive layer and an upper surface which is not in contact with the insulating layer;
a second conductive layer which is in contact with the second pad in the insulating layer; and
a fourth pad including a lower surface which is in contact with an upper surface of the second conductive layer and an upper surface which is not in contact with the insulating layer.
13 . The storage wafer according to claim 9 , further comprising:
an insulating layer provided on upper surfaces of the first element layer and the second element layer;
a first conductive layer which is in contact with the first pad in the insulating layer;
a second conductive layer which is in contact with the second pad in the insulating layer; and
a third conductive layer which is in contact with the first conductive layer and the second conductive layer; and
a fifth pad including a lower surface which is in contact with an upper surface of the third conductive layer and an upper surface which is not in contact with the insulating layer.
14 . A manufacturing method of a storage wafer, comprising:
forming a first plurality of chip units on a first wafer;
forming a second plurality of chip units on a second wafer;
determining whether a condition is satisfied with respect to each of the first plurality of chip units and the second plurality of chip units;
specifying a first chip unit included in the first plurality of chip units and determined as satisfying the condition, a second chip unit included in the first plurality of chip units and determined as failing to satisfy the condition, and a third chip unit included in the second plurality of chip units and determined as satisfying the condition;
dicing the second wafer into each of the second plurality of chip units; and
mounting the third chip unit on an upper surface of the second chip unit via a first adhesive film, wherein
a first pad provided on the first chip unit and a second pad provided on the second chip unit are provided in substantially a same plane, and
the second pad is electrically isolated from an external electrode by the first adhesive film, the external electrode being provided on an outside of the first wafer.
15 . The manufacturing method according to claim 14 , further comprising:
determining defectiveness with respect to each of the first plurality of chip units which are formed on the first wafer and on which the third chip unit is not mounted;
specifying a fourth chip unit included in the first plurality of chip units and determined as being defective, and a fifth chip unit, different from the third chip unit, included in the second plurality of chip units and determined as satisfying the condition; and
remounting the fifth chip unit on an upper surface of the fourth chip unit via a second adhesive film.
16 . A manufacturing method of a storage wafer, comprising:
forming a first plurality of chip units on a first wafer;
forming a second plurality of chip units on a second wafer;
determining whether a condition is satisfied with respect to each of the first plurality of chip units and the second plurality of chip units;
specifying a first chip unit included in the first plurality of chip units and determined as satisfying the condition, a second chip unit included in the first plurality of chip units and determined as failing to satisfy the condition, and a third chip unit included in the second plurality of chip units and determined as satisfying the condition;
dicing the second wafer into each of the second plurality of chip units;
removing the second chip unit from the first wafer; and
mounting the third chip unit on a first region where the second chip unit has been removed via an adhesive film, wherein
a first pad provided on the first chip unit and a third pad provided on the mounted third chip unit are provided in substantially a same plane.
17 . The manufacturing method according to claim 16 , further comprising:
determining defectiveness with respect to each of the first plurality of chip units which are formed on the first wafer and on which the third chip unit is not mounted;
specifying a fourth chip unit included in the first plurality of chip units and determined as being defective, and a fifth chip unit, different from the third chip unit, included in the second plurality of chip units and determined as satisfying the condition;
removing the fourth chip unit from the first wafer; and
remounting the fifth chip unit on a second region where the fourth chip unit has been removed via a second adhesive film.