Apparatus and method for multi-die interconnection

1. A method of fabricating a semiconductor having multiple, interconnected die, the method comprising:

providing a semiconductor substrate having:

a plurality of disparate die formed within the semiconductor substrate, and

a plurality of scribe lines defined by an area between pairs of adjacent die of the plurality of disparate die; and

fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die,

wherein fabricating the plurality of inter-die connections includes:

setting a position of a die reticle offset a center of each die of each adjacent pair of die;

setting the die reticle overlapping a first circuitry region of a first die of each adjacent pair of die and a second circuitry region of a second die of each adjacent of pair of die, wherein the die reticle comprises geometries for forming the plurality of inter-die connections; and

upon setting the die reticle into position, exposing by the lithography system the die reticle thereby forming the plurality of inter-die connections between adjacent pair of die.

2. The method according to claim 1 , further comprising:

providing a protective barrier at each of the plurality of die that surrounds active circuit regions of each of the plurality of disparate die.

3. The method according to claim 1 , further comprising:

identifying a largest usable geometry of the semiconductor substrate that includes an array or subset of the plurality of die; and

fabricating a circuitry layer only at each of the plurality of die within the identified largest usable geometry.

4. The method according to claim 1 , further comprising:

fabricating one or more circuitry layers on each of the plurality of die.

5. The method according to claim 1 , wherein:

each of the plurality of inter-die connections extend from a first circuitry region of a first die of each adjacent pair of die to a second circuitry region of a second die of each adjacent of pair of die.

6. The method according to claim 1 , wherein:

fabricating the plurality of inter-die connections includes:

setting a position of a first die reticle centered with a first die of each adjacent pair of die;

setting a position of a second die reticle centered with a second die of each adjacent pair,

wherein the position of the second die reticle overlaps a portion of the first die reticle, and

wherein the first die reticle and the second die reticle comprise geometries for forming the plurality of inter-die connections between each adjacent pair of die;

upon setting the first die reticle into position, exposing by the lithography system the first die reticle thereby forming a first portion of each of the plurality of inter-die connections between adjacent pair of die; and

upon setting the second die reticle into position, exposing by the lithography system the second die reticle thereby forming a second portion of each of the plurality of inter-die connections between adjacent pair of die.

7. A method of fabricating a semiconductor having multiple, interconnected die, the method comprising:

providing a semiconductor substrate having:

a plurality of disparate die formed within the semiconductor substrate, and

a plurality of scribe lines defined by an area between pairs of adjacent die of the plurality of disparate die; and

fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die,

wherein fabricating the plurality of inter-die connections includes:

setting a position of a first die reticle centered with a first die of each adjacent pair of die;

setting a position of a second die reticle centered with a second die of each adjacent pair,

wherein the position of the second die reticle overlaps a portion of the first die reticle, and

wherein the first die reticle and the second die reticle comprise geometries for forming the plurality of inter-die connections between each adjacent pair of die;

upon setting the first die reticle into position, exposing by the lithography system the first die reticle thereby forming a first portion of each of the plurality of inter-die connections between adjacent pair of die; and

upon setting the second die reticle into position, exposing by the lithography system the second die reticle thereby forming a second portion of each of the plurality of inter-die connections between adjacent pair of die.

8. The method according to claim 7 , further comprising:

providing a protective barrier at each of the plurality of die that surrounds active circuit regions of each of the plurality of disparate die.

9. The method according to claim 7 , further comprising:

identifying a largest usable geometry of the semiconductor substrate that includes an array or subset of the plurality of die; and

fabricating a circuitry layer only at each of the plurality of die within the identified largest usable geometry.

10. The method according to claim 7 , further comprising:

fabricating one or more circuitry layers on each of the plurality of die.

11. The method according to claim 7 , wherein:

each of the plurality of inter-die connections extend from a first circuitry region of a first die of each adjacent pair of die to a second circuitry region of a second die of each adjacent of pair of die.

12. The method according to claim 7 , wherein:

fabricating the plurality of inter-die connections includes:

setting a position of a die reticle offset a center of each die of each adjacent pair of die;

setting the die reticle overlapping a first circuitry region of a first die of each adjacent pair of die and a second circuitry region of a second die of each adjacent of pair of die, wherein the die reticle comprises geometries for forming the plurality of inter-die connections; and

upon setting the die reticle into position, exposing by the lithography system the die reticle thereby forming the plurality of inter-die connections between adjacent pair of die.

13. A method of fabricating a semiconductor having multiple, interconnected die, the method comprising:

providing a semiconductor substrate having:

a plurality of disparate die formed within the semiconductor substrate, and

a plurality of scribe lines defined by an area between pairs of adjacent die of the plurality of disparate die; and

fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die,

wherein fabricating the plurality of inter-die connections includes:

forming a first portion of each of the plurality of inter-die connections between adjacent pair of die;

forming a second portion of each of the plurality of inter-die connections between adjacent pair of die,

wherein the second portion comprises a second layer of conductive material that overlaps the first portion comprising a first layer of conductive material, and

wherein each of the plurality of inter-die connections is defined by the overlap of the first layer and the second layer.

14. The method according to claim 13 , further comprising:

providing a protective barrier at each of the plurality of die that surrounds active circuit regions of each of the plurality of disparate die.

15. The method according to claim 13 , further comprising:

identifying a largest usable geometry of the semiconductor substrate that includes an array or subset of the plurality of die; and

fabricating a circuitry layer only at each of the plurality of die within the identified largest usable geometry.

16. The method according to claim 13 , further comprising:

fabricating one or more circuitry layers on each of the plurality of die.

17. The method according to claim 13 , wherein:

each of the plurality of inter-die connections extend from a first circuitry region of a first die of each adjacent pair of die to a second circuitry region of a second die of each adjacent of pair of die.

18. The method according to claim 13 , wherein:

fabricating the plurality of inter-die connections includes:

setting a position of a die reticle offset a center of each die of each adjacent pair of die;

setting the die reticle overlapping a first circuitry region of a first die of each adjacent pair of die and a second circuitry region of a second die of each adjacent of pair of die, wherein the die reticle comprises geometries for forming the plurality of inter-die connections; and

upon setting the die reticle into position, exposing by the lithography system the die reticle thereby forming the plurality of inter-die connections between adjacent pair of die.

19. The method according to claim 13 , wherein:

fabricating the plurality of inter-die connections includes:

setting a position of a first die reticle centered with a first die of each adjacent pair of die;

setting a position of a second die reticle centered with a second die of each adjacent pair,

wherein the position of the second die reticle overlaps a portion of the first die reticle, and

wherein the first die reticle and the second die reticle comprise geometries for forming the plurality of inter-die connections between each adjacent pair of die;

upon setting the first die reticle into position, exposing by the lithography system the first die reticle thereby forming a first portion of each of the plurality of inter-die connections between adjacent pair of die; and

upon setting the second die reticle into position, exposing by the lithography system the second die reticle thereby forming a second portion of each of the plurality of inter-die connections between adjacent pair of die.

20. The method according to claim 13 , wherein:

a width of an overlapping portion of the first and second layers are diminished relative to a width of a non-overlapping portion of non-overlapping portions of each of the first and second layers.