Memory system including nonvolatile memory
According to one embodiment, in response to receiving a read command from a host, a controller executes a command process of reading data from a nonvolatile memory. The controller executes an address translation process of translating a virtual address specified in the read command to a physical address for accessing a memory of the host. In the address translation process, the controller transmits an address translation request to the host. In response to receiving from the host a response indicating that obtainment of address translation information fails, the controller suspends the command process until the address translation information is obtained, and after the address translation information is obtained, resumes the command process.
1. A memory system connectable to a host, comprising:
a nonvolatile memory; and
a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein
the controller is configured to:
in response to obtaining a first I/O command from one of a plurality of submission queues stored in a memory of the host,
execute a command process of writing or reading data to or from the nonvolatile memory,
execute an address translation process of translating a first virtual address in a virtual address space of the host to a first physical address for accessing the memory of the host, the first virtual address being a virtual address corresponding to a memory location in the memory of the host to which first information is to be transferred, the first information being information for notifying the host of completion of the first I/O command,
in the address translation process, transmit an address translation request to the host, the address translation request being a request for obtaining first address translation information for translating the first virtual address to the first physical address, and
in response to receiving, from the host, a response indicating that obtainment of the first address translation information fails, suspend a first process of fetching an I/O command from one or more first submission queues in the memory of the host among the plurality of submission queues until the first address translation information is obtained, each of the one or more first submission queues being a submission queue associated with a first completion queue in the memory of the host in which a completion response of the first I/O command is to be stored, and, after the first address translation information is obtained, resume the first process.
2. The memory system of claim 1 , wherein
the controller is configured to:
in response to receiving, from the host, a response indicating that the obtainment of the first address translation information fails,
suspend the first process;
transmit, to the host, a message requesting preparation of the first address translation information;
in response to receiving, from the host, a response indicating completion of the preparation of the first address translation information, transmit the address translation request to the host again; and
in response to receiving, from the host, the response indicating the completion of the preparation of the first address translation information or a response to the re-transmitted address translation request, the response to the re-transmitted address translation request including the first address translation information, resume the first process.
3. The memory system of claim 1 , wherein
the controller is configured to:
when the address translation process succeeds, transfer the first information to the memory of the host using the first physical address; and
when the address translation process fails, suspend the first process, and, after the address translation process succeeds, resume the first process.
4. The memory system of claim 1 , further comprising a cache memory, wherein
the controller is configured to:
in the address translation process, when detecting that the first address translation information is not stored in the cache memory,
suspend the first process;
transmit the address translation request to the host; and
in response to receiving, from the host, a response to the address translation request, the response to the address translation request including the first address translation information, resume the first process.
5. The memory system of claim 4 , wherein
the controller is configured to:
in response to receiving, from the host, an invalidation request specifying the first virtual address,
invalidate the first address translation information in the cache memory; and
suspend the first process until new address translation information corresponding to the first virtual address is obtained from the host.
6. The memory system of claim 1 , wherein
the first information includes the completion response of the first I/O command, and
the first virtual address is a virtual address corresponding to a memory location in the memory of the host where the first completion queue is stored.
7. The memory system of claim 1 , wherein
the first information includes an interrupt message for notifying the host that the completion response of the first I/O command has been stored in the first completion queue, and
the first virtual address is a virtual address corresponding to a memory location in the memory of the host to which the interrupt message is to be transferred.