Display device having optimized ratios of channel width to channel length of transistors
A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W 1 to a channel length L 1 of the first transistor (a W 1 /L 1 ratio) and a ratio of a channel width W 2 to a channel length L 2 of the second transistor (a W 2 /L 2 ratio) are larger than a ratio of a channel width W 3 to a channel length L 3 of the third transistor (a W 3 /L 3 ratio) and a ratio of a channel width W 4 to a channel length L 4 of the fourth transistor (a W 4 /L 4 ratio).
1 . A display device comprising:
a light-emitting element;
a first transistor and a second transistor connected in series between the light-emitting element and a driving power line;
a third transistor electrically connected to a gate electrode of the first transistor;
a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element; and
a holding capacitor connected between the gate electrode and the drain electrode of the first transistor,
wherein a ratio of a channel width W 1 to a channel length L 1 of the first transistor (a W 1 /L 1 ratio) and a ratio of a channel width W 2 to a channel length L 2 of the second transistor (a W 2 /L 2 ratio) are larger than a ratio of a channel width W 3 to a channel length L 3 of the third transistor (a W 3 /L 3 ratio) and a ratio of a channel width W 4 to a channel length L 4 of the fourth transistor (a W 4 /L 4 ratio).
2 . The display device according to claim 1 , wherein the W 1 /L 1 ratio of the first transistor and the W 2 /L 2 ratio of the second transistor are 1.5 or more, and the W 3 /L 3 ratio of the third transistor and the W 4 /L 4 ratio of the fourth transistor are less than 1.5.
3 . The display device according to claim 1 , further comprising:
a fifth transistor electrically connected to the gate electrode of the first transistor,
wherein the W 1 /L 1 ratio of the first transistor is larger than a ratio of a channel width W 5 to a channel length L 5 of the fifth transistor (a W 5 /L 5 ratio).
4 . The display device according to claim 3 , wherein
the W 1 /L 1 ratio of the first transistor and the W 2 /L 2 ratio of the second transistor are 1.5 or more, and
the W 5 /L 5 ratio of the fifth transistor is less than 1.5.
5 . The display device according to claim 2 , wherein the W 3 /L 3 ratio of the third transistor is the same as the W 4 /L 4 ratio of the fourth transistor.
6 . The display device according to claim 1 , wherein the channel length L 1 of the first transistor is different from the channel length L 3 of third transistor and the channel length L 4 of the fourth transistor.
7 . A display device comprising:
a high potential power source;
a low potential power source;
a light-emitting element including an anode and a cathode, the cathode being connected to the low potential power source;
a first transistor including a source electrode, a drain electrode and a gate electrode, the drain electrode of the first transistor being connected to the anode of the light-emitting element;
a second transistor including a source electrode, a drain electrode and a gate electrode, the drain electrode of the second transistor being connected to the source electrode of the first transistor, and the source electrode of the second transistor being connected to the high potential power source;
a third transistor including a source electrode, a drain electrode and a gate electrode, the drain electrode of the third transistor being connected to the gate electrode of the first transistor; and
a fourth transistor including a source electrode, a drain electrode and a gate electrode, the drain electrode of the fourth transistor being connected to the drain electrode of the first transistor and the anode of the light-emitting element,
wherein
a ratio of a channel width W 1 to a channel length L 1 of the first transistor (a W 1 /L 1 ratio) and a ratio of a channel width W 2 to a channel length L 2 of the second transistor (a W 2 /L 2 ratio) are larger than a ratio of a channel width W 3 to a channel length L 3 of the third transistor (a W 3 /L 3 ratio) and a ratio of a channel width W 4 to a channel length L 4 of the fourth transistor (a W 4 /L 4 ratio).
8 . The display device according to claim 7 , further comprising:
a holding capacitor connected between the gate electrode of the first transistor and the drain electrode of the first transistor.
9 . The display device according to claim 8 , wherein
the holding capacitor is connected between the drain electrode of the third transistor and the drain electrode of the fourth transistor.
10 . The display device according to claim 9 , further comprising:
an emission control scanning line,
wherein
the gate electrode of the second transistor is connected to the emission control scanning line, and
the second transistor controls an emission time of the light-emitting element in response to a control signal from the emission control scanning line.
11 . The display device according to claim 10 , further comprising:
a write control scanning line; and
a video signal line,
wherein
the gate electrode of the third transistor is connected to the write control scanning line,
the write control scanning line writes a control signal to the gate electrode of the third transistor,
the source electrode of the third transistor is connected to the video signal line,
the video signal line writes a video signal to the source electrode of the third transistor, and
the third transistor writes a voltage corresponding to a luminance of the light-emitting element to the gate electrode of the first transistor.
12 . The display device according to claim 11 , wherein
the first transistor is connected in series with the light-emitting element and the second transistor between the high potential power source and the low potential power source, and
the first transistor controls a current value flowing to the light-emitting element.
13 . The display device according to claim 12 , further comprising:
a reset control scanning line; and
a reset power source line,
wherein
the gate electrode of the fourth transistor is connected to the reset control scanning line,
a control signal from the reset control scanning line switches the fourth transistor between an ON state and an OFF state,
the source electrode of the fourth transistor is connected to the reset power source line,
the reset power source line is fixed to a reset potential, and
a potential of the drain electrode of the first transistor is initialized when the fourth transistor is turned ON.
14 . The display device according to claim 13 , further comprising:
an initialization scanning line;
an initialization signal line; and
a fifth transistor including a source electrode, a drain electrode and a gate electrode,
the drain electrode of the fifth transistor being connected to the gate electrode of the first transistor, the drain electrode of the third transistor and the holding capacitor,
the source electrode of the fifth transistor being connected to the initialization signal line, and
the gate electrode of the fifth transistor being connected to the initialization scanning line,
wherein
a control signal from the initialization scanning line switches the fifth transistor between an ON state and an OFF state,
the gate electrode of the first transistor is fixed to an initialization potential through the fifth transistor when the fifth transistor is turned ON.
15 . The display device according to claim 7 , wherein
the first transistor and the second transistor control a current flowing to the light-emitting element.
16 . A display device comprising:
a light-emitting element;
a first transistor and a second transistor connected in series between the light-emitting element and a driving power line;
a third transistor electrically connected to a gate electrode of the first transistor; and
a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element,
wherein
a ratio of a channel width W 1 to a channel length L 1 of the first transistor (a W 1 /L 1 ratio) and a ratio of a channel width W 2 to a channel length L 2 of the second transistor (a W 2 /L 2 ratio) are larger than a ratio of a channel width W 3 to a channel length L 3 of the third transistor (a W 3 /L 3 ratio) and a ratio of a channel width W 4 to a channel length L 4 of the fourth transistor (a W 4 /L 4 ratio), and
the first transistor and the second transistor control a current flowing to the light-emitting element.
17 . The display device according to claim 16 , wherein
the first transistor, the second transistor, the third transistor and the fourth transistor are formed of oxide semiconductor.
18 . The display device according to claim 17 , wherein
the first transistor controls a current value flowing to the light-emitting element, and
the second transistor controls an emission time of the light-emitting element.
19 . The display device according to claim 18 , wherein
the third transistor writes a voltage corresponding to a luminance of the light-emitting element to a gate electrode of the first transistor, and
the fourth transistor initializes a potential of the drain electrode of the first transistor to a predetermined potential.
20 . The display device according to claim 19 , further comprising:
a fifth transistor electrically connected to the gate electrode of the first transistor,
wherein the W 1 /L 1 ratio of the first transistor is larger than a ratio of a channel width W 5 to a channel length L 5 of the fifth transistor (a W 5 /L 5 ratio),
the fifth transistor is formed of oxide semiconductor, and
the fifth transistor fixes a potential of the gate electrode of the first transistor to a predetermined potential.