Semiconductor structures with reduced parasitic capacitance and methods for forming the same
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.
1 . A method, comprising:
forming a dummy gate stack engaging a semiconductor fin over a substrate;
conformally depositing a first dielectric layer over the substrate;
conformally depositing a second dielectric layer over the first dielectric layer;
etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer;
forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack; and
replacing the dummy gate stack with a gate structure,
wherein a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.
2 . The method of claim 1 , wherein a density of the first dielectric layer is greater than 1.7 g/cm 3 .
3 . The method of claim 1 , wherein each of the first dielectric layer and the second dielectric layer comprises an oxygen-free dielectric material.
4 . The method of claim 1 , wherein the first dielectric layer comprises boron nitride having a hexagonal ring structure.
5 . The method of claim 1 , further comprising:
after the forming of the source/drain features, forming a bi-layer etch stop layer over the substrate, wherein the forming of the bi-layer etch stop layer comprises:
depositing a first material layer over the substrate, and
depositing a second material layer over the first material layer, wherein the first material layer comprises boron nitride, and the second material layer comprises silicon nitride or silicon carbonitride,
depositing an interlayer dielectric layer over the bi-layer etch stop layer; and
performing a planarization process until a top surface of the interlayer dielectric layer is coplanar with a top surface of a dummy gate electrode layer in the dummy gate stack.
6 . The method of claim 1 , wherein the semiconductor fin is a first semiconductor fin and extends lengthwise along a first direction, the gate structure extends lengthwise along a second direction substantially perpendicular to the first direction and further engages a second semiconductor fin and a third semiconductor fin, wherein the method further comprises:
forming a first trench and a second trench extending through the gate structure, wherein the first trench is disposed between the first semiconductor fin and the second semiconductor fin, and the second trench is disposed between the second semiconductor fin and the third semiconductor fin;
depositing a first dielectric material layer in the first trench and the second trench;
depositing a second dielectric material layer over the first dielectric material layer;
depositing a third dielectric material layer over the second dielectric material layer to substantially fill remaining portions of the first trench and the second trench; and
performing a planarization process to form a first isolation structure in the first trench and a second isolation structure in the second trench,
wherein a dielectric constant of the first dielectric material layer is less than a dielectric constant of the third dielectric material layer, and the dielectric constant of the third dielectric material layer is less than a dielectric constant of the second dielectric material layer.
7 . The method of claim 6 , wherein the first semiconductor fin is spaced apart from the second semiconductor fin by a first isolation feature, and the second semiconductor fin is spaced apart from the third semiconductor fin by a second isolation feature, the first isolation structure extends into the first isolation feature, and the second isolation structure extends into the second isolation feature.
8 . The method of claim 6 , further comprising:
after the forming of the first isolation structure and the second isolation structure, selectively removing a portion of the gate structure engaging the second semiconductor fin to form a third trench;
selectively removing a portion of the second semiconductor fin directly under the portion of the gate structure to extend the third trench; and
forming a third isolation structure in the third trench.
9 . The method of claim 8 , wherein the forming of the third isolation structure comprises:
performing a first deposition process to conformally deposit a boron nitride layer; and
performing a second deposition process to deposit a silicon nitride layer over the boron nitride layer, wherein the first deposition process and the second deposition process are performed in a same process chamber.
10 . A method, comprising:
receiving a workpiece comprising:
an active region over a substrate and comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, the active region comprising a channel region and a source/drain region adjacent the channel region, and
a dummy gate stack over the channel region;
selectively recessing the source/drain region to form a source/drain opening exposing the plurality of sacrificial layers and the plurality of channel layers;
selectively recessing the plurality of sacrificial layers to form inner spacer recesses;
conformally depositing a first dielectric layer over the workpiece;
conformally depositing a second dielectric layer over the first dielectric layer;
etching back the first dielectric layer and the second dielectric layer to form inner spacer features in the inner spacer recesses, the inner spacer features comprising the first dielectric layer and the second dielectric layer;
forming a source/drain feature in the source/drain opening;
selectively removing the dummy gate stack;
selectively removing the plurality of sacrificial layers; and
forming a gate structure to wrap around each channel layer of the plurality of channel layers,
wherein the first dielectric layer comprises a silicon-free low-k dielectric material, and the second dielectric layer comprises an oxygen-free dielectric material and is less easily to be oxidized than the first dielectric layer.
11 . The method of claim 10 , wherein a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and a dielectric constant of the second dielectric layer is greater than the dielectric constant of silicon oxide.
12 . The method of claim 10 , wherein the first dielectric layer comprises boron nitride, and the second dielectric layer comprises in-situ formed silicon nitride or in-situ formed silicon carbonitride.
13 . The method of claim 10 , further comprising:
after the forming of the source/drain feature, conformally depositing a first material layer over the workpiece;
conformally depositing a second material layer over the first material layer; and
depositing an interlayer dielectric layer over the second material layer,
wherein the first material layer comprises a silicon-free and oxygen-free material, and the second material layer is less easily to be oxidized than the first material layer.
14 . The method of claim 10 , wherein the workpiece further comprises a gate spacer extending along a sidewall surface of the dummy gate stack, wherein the gate spacer comprises boron nitride.
15 . The method of claim 10 , further comprising: forming a gate isolation structure to cut the gate structure into pieces, wherein the gate isolation structure comprises a boron nitride liner.
16 . The method of claim 10 , further comprising: forming a dielectric gate extending into the substrate, wherein a bottom surface of the dielectric gate is lower than a bottom surface of the channel region, and wherein the dielectric gate comprises boron nitride.
17 . A semiconductor structure, comprising:
a first transistor comprising:
a first vertical stack of channel members disposed over a substrate;
a first gate structure wrapping around the first vertical stack of channel members;
a first source/drain feature coupled to the first vertical stack of channel members and adjacent the first gate structure;
a plurality of inner spacer features laterally disposed between the first source/drain feature and the first gate structure; and
a gate spacer extending along a sidewall surface of the first gate structure and over the first vertical stack of channel members,
wherein, each inner spacer feature of the plurality of inner spacer features comprises a first dielectric layer and a second dielectric layer, the first dielectric layer comprises boron nitride, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.
18 . The semiconductor structure of claim 17 , wherein the second dielectric layer comprises silicon nitride or silicon carbonitride.
19 . The semiconductor structure of claim 17 , further comprising:
a second transistor stacked over the first transistor and comprising a second source/drain feature, wherein, in a perspective view, the second source/drain feature is electrically coupled to the first source/drain feature via an L-shape conductive feature.
20 . The semiconductor structure of claim 17 , further comprising:
a contact etch stop layer over the first source/drain feature and extending along the gate spacer; and
an interlayer dielectric layer on the contact etch stop layer,
wherein a composition of the contact etch stop layer is the same as a composition of the gate spacer.