Semiconductor package and method of manufacturing the semiconductor package
A semiconductor package includes a package substrate, a chip stack structure on the package substrate, the chip stack structure including a base chip having a first thickness and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness, and a sealing member on an upper surface of the package substrate and on the chip stack structure. At least one of the plurality of upper chips includes a chip substrate having opposite first and second surfaces, a circuit layer on the first surface, and a stress compensation layer on the second surface and having an internal stress that offsets a warpage of the chip substrate.
1. A semiconductor package, comprising:
a package substrate;
a chip stack structure on the package substrate, the chip stack structure comprising a base chip having a first thickness, and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness; and
a sealing member on an upper surface of the package substrate and on the chip stack structure;
wherein at least one of the plurality of upper chips comprises:
a chip substrate having opposite first and second surfaces;
a circuit layer on the first surface; and
a stress compensation layer on the second surface, wherein the stress compensation layer has an internal stress that offsets a warpage of the chip substrate.
2. The semiconductor package of claim 1 , wherein the second thickness of each of the plurality of upper chips is within a range of about 15 μm to 40 μm.
3. The semiconductor package of claim 1 , wherein the chip substrate of the at least one of the plurality of upper chips has a thickness within a range of about 5 μm to 15 μm, the circuit layer has a thickness within a range of about 15 μm to 35 μm, and the stress compensation layer has a thickness within a range of about 0.01 μm to 1 μm.
4. The semiconductor package of claim 1 , wherein the stress compensation layer comprises silicon oxide, silicon nitride or silicon oxynitride.
5. The semiconductor package of claim 1 , wherein the stress compensation layer is on an entirety of the second surface of the chip substrate of the at least one of the plurality of upper chips.
6. The semiconductor package of claim 1 , wherein the plurality of upper chips are sequentially attached to the base chip via adhesive film between adjacent ones of the plurality of upper chips and between a lowermost one of the plurality of upper chips and the base chip.
7. The semiconductor package of claim 1 , further comprising:
a plurality of conductive connection members electrically connecting chip pads of the base chip and the plurality of upper chips to substrate pads of the package substrate.
8. The semiconductor package of claim 7 , wherein the plurality of upper chips are on the package substrate such that the second surface of the chip substrate of the at least one of the plurality of upper chips faces the package substrate.
9. The semiconductor package of claim 1 , further comprising:
a first semiconductor chip on the package substrate, and
wherein the base chip is attached on top of the first semiconductor chip.
10. The semiconductor package of claim 9 , wherein the first semiconductor chip comprises a logic chip, and the base chip and the plurality of upper chips each comprise a memory chip.
11. A semiconductor package, comprising:
a package substrate;
a semiconductor chip on an upper surface of the package substrate;
a support spacer on the upper surface of the package substrate and spaced apart from the semiconductor chip;
a chip stack structure on the semiconductor chip and the support spacer, the chip stack structure comprising a base chip having a first thickness and a plurality of upper chips sequentially stacked on the base chip, wherein the plurality of upper chips each have a second thickness smaller than the first thickness; and
a sealing member on the upper surface of the package substrate, on the semiconductor chip, on the support spacer, and on the chip stack structure,
wherein each of the plurality of upper chips comprises:
a chip substrate having opposite first and second surfaces;
a circuit layer on the first surface; and
a stress compensation layer on the second surface and comprising an internal stress that offsets an internal stress of the chip substrate.
12. The semiconductor package of claim 11 , wherein the chip substrate of each of the plurality of upper chips has a thickness within a range of about 5 μm to 15 μm, the circuit layer of each of the plurality of upper chips has a thickness within a range of about 15 μm to 35 μm, and the stress compensation layer of each of the plurality of upper chips has a thickness within a range of about 0.01 μm to 1 μm.
13. The semiconductor package of claim 11 , wherein the stress compensation layer of each of the plurality of upper chips comprises silicon oxide, silicon nitride or silicon oxynitride.
14. The semiconductor package of claim 11 , further comprising:
a plurality of conductive connection members electrically connecting chip pads of the base chip and the plurality of upper chips to substrate pads of the package substrate.
15. The semiconductor package of claim 11 , wherein the semiconductor chip comprises a logic chip, and the base chip and the plurality of upper chips each comprise a memory chip.
16. A method of manufacturing a semiconductor package, the method comprising:
providing a first wafer having a first thickness;
providing a second wafer having a second thickness less than the first thickness;
dicing the first wafer to form a base chip;
forming a stress compensation layer on a backside surface of the second wafer, the stress compensation layer comprising an internal stress selected to offset an internal stress within the second wafer;
dicing the second wafer to form a plurality of upper chips;
attaching the base chip to an upper surface of a package substrate;
sequentially stacking the plurality of upper chips on the base chip; and
forming a sealing member on the upper surface of the package substrate, on the base chip, and on the plurality of upper chips.
17. The method of claim 16 , wherein the forming the stress compensation layer comprises performing a sputtering process or a plasma deposition process on the backside surface of the second wafer.
18. The method of claim 16 , wherein the sequentially stacking of the plurality of upper chips on the base chip comprises attaching the plurality of upper chips to the package substrate such that the stress compensation layer on each of the plurality of upper chips faces the package substrate.
19. The method of claim 18 , wherein the sequentially stacking of the plurality of upper chips on the base chip comprises attaching the plurality of upper chips to the base chip using adhesive film between adjacent ones of the plurality of upper chips and between a lowermost one of the plurality of upper chips and the base chip.
20. The method of claim 16 , further comprising:
electrically connecting chip pads of the base chip and the plurality of upper chips to substrate pads of the package substrate using a plurality of conductive connecting members.