Semiconductor device and manufacturing method thereof
A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.
1 . A method comprising:
forming a dummy gate over a semiconductor fin;
forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate;
depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure;
replacing the dummy gate with a gate structure;
forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer;
recessing the portion of the dielectric structure embedded in the ILD layer;
removing polymers formed on surfaces of the ILD layer after recessing the portion of the dielectric structure;
after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and
forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.
2 . The method of claim 1 , wherein recessing the portion of the dielectric structure embedded in the ILD layer is performed until a top surface of the portion of the dielectric structure is lower than or substantially coplanar with a level at which the source/drain epitaxial structure has a largest horizontal width.
3 . The method of claim 1 , wherein removing the polymers formed on surfaces of the ILD layer is further performed prior to removing the portion of the ILD layer over the source/drain epitaxial structure.
4 . The method of claim 1 , wherein the source/drain epitaxial structure has a first facet and a second facet both facing the dielectric structure, the first facet is over the second facet, and removing the portion of the ILD layer over the source/drain epitaxial structure is such that the first facet is exposed while the second facet is covered by the ILD layer.
5 . The method of claim 1 , wherein the source/drain epitaxial structure has a first facet and a second facet both facing the dielectric structure, the first facet is over the second facet, and an interface between the portion of the dielectric structure and the source/drain contact is lower than a joint of the first facet and the second facet.
6 . The method of claim 1 , wherein the dielectric structure comprises:
an oxide-rich layer; and
a nitride-rich layer wrapping the oxide-rich layer.
7 . The method of claim 1 , wherein removing the polymers is performed by using a mixture of N 2 , H 2 , and O 3 gases as etching gases.
8 . A method comprising:
forming a transistor over a substrate, wherein the transistor comprises:
a gate structure;
a source/drain epitaxial structure adjacent to the gate structure;
a contact etch stop layer (CESL) covering the source/drain epitaxial structure; and
a first interlayer dielectric (ILD) layer covering the CESL;
forming a dielectric structure over the substrate, wherein the dielectric structure is in contact with the gate structure and partially embedded in the first ILD layer;
forming a second ILD layer over the transistor and the dielectric structure;
forming a contact opening in the second ILD layer and over the dielectric structure;
performing a first etching process to deepen the contact opening, wherein the first etching process etches the dielectric structure faster than etches the first ILD layer;
performing a second etching process to further deepen the contact opening and expose the source/drain epitaxial structure;
performing a third etching process after performing the second etching process, wherein the third etching process etches the CESL faster than etches the source/drain epitaxial structure; and
forming a source/drain contact in the contact opening.
9 . The method of claim 8 , wherein the source/drain epitaxial structure has a first facet and a second facet both facing the dielectric structure, after performing the second etching process, a portion of the CESL covers the first facet, and after performing the third etching process, an entirety of the first facet is exposed by the CESL.
10 . The method of claim 8 , wherein the third etching process is performed by using a gaseous mixture of a fluorine-containing gas and a hydrogen-containing gas.
11 . The method of claim 8 , wherein the first etching process is performed by using a gaseous mixture of a fluorine-containing gas and a hydrogen-containing gas.
12 . The method of claim 8 , wherein a hydrogen concentration of a gas mixture used in the first etching process is higher than a hydrogen concentration of a gas mixture used in the second etching process.
13 . The method of claim 8 , wherein a vertical thickness of a first portion of the source/drain contact directly over the dielectric structure is greater than a vertical thickness of a second portion of the source/drain contact directly over the source/drain epitaxial structure.
14 . A method comprising:
forming a dummy gate structure over a channel structure of a substrate;
epitaxially depositing a source/drain structure on a sidewall of the channel structure;
depositing a contact etch stop layer (CESL) to cover the source/drain structure;
depositing an interlayer dielectric (ILD) layer over the CESL and laterally surrounding the dummy gate structure;
replacing the dummy gate structure with a metal gate structure, wherein the metal gate structure extends in a first direction in a top view;
forming a dielectric structure in the ILD layer and in contact with the metal gate structure, wherein the dielectric structure extends in a second direction different from the first direction;
recessing the dielectric structure to form a first recess in the dielectric structure, wherein the first recess is defined by inner sidewalls of the ILD layer;
after recessing the dielectric structure, recessing the ILD layer and the CESL to form a second recess in the ILD layer and the CESL and communicating with the first recess, wherein the second recess exposes the source/drain structure, and a bottom of the first recess is lower than a bottom of the second recess; and
forming a source/drain contact in the first recess and the second recess.
15 . The method of claim 14 , further comprising:
removing a polymer layer formed on the inner sidewalls of the ILD layer prior to recessing the ILD layer and the CESL.
16 . The method of claim 14 , wherein after recessing the ILD layer and the CESL, a top surface of the CESL is higher than the bottom of the first recess.
17 . The method of claim 14 , wherein the first recess is deepened during recessing the ILD layer and the CESL.
18 . The method of claim 14 , further comprising after recessing the ILD layer and the CESL, removing portions of the ILD layer and the CESL on a sidewall of the source/drain structure.
19 . The method of claim 18 , wherein a plasma frequency used in removing the portions of the ILD layer and the CESL on the sidewall of the source/drain structure is higher than a plasma frequency used in recessing the ILD layer and the CESL.
20 . The method of claim 8 , wherein the third etching process is a plasma etching process.