IP Library Granted Patent US 12,745,580
Granted Patent B2
US 12,745,580 · App. 18/190,085 · Granted Sep 22, 2026

Self-aligned litho-etch-litho-etch mandrel cut process for advanced FINFET interconnect

Inventors: Xiaoming Yang (Clifton Park, NY); Lawrence A. Clevenger (Saratoga Springs, NY)
Assignee: International Business Machines Corporation
H10P50/73H10W20/089H10W20/43H10W20/48
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Quick Facts
Patent No.
US 12,745,580
App. No.
18/190,085
Granted
Sep 22, 2026
Kind
B2
Abstract

A method of fabricating a semiconductor device, includes providing a semiconductor structure having a dielectric stack and a mandrel layer positioned on the dielectric stack. An array of sacrificial mandrel features are patterned into the mandrel layer and on top of an insulating layer of the dielectric stack. A self-aligned non-mandrel cut is formed adjacent a spacer element located adjacent to one of the sacrificial mandrel features. The sacrificial mandrel features are removed. One or more self-aligned mandrel cuts are formed in one or more of the plurality of trenches. Non-mandrel openings are formed on top of the insulating layer. Continuity line openings are etched into the dielectric stack, wherein the non-mandrel cut interrupts a first of the continuity line openings and the mandrel cut is disposed to interrupt a second of the continuity line openings. Metal lines are formed in the continuity line openings, except where the non-mandrel cut and mandrel cut are disposed.

Claims (31)

1 . A method of fabricating a semiconductor device, comprising:

providing a semiconductor structure having a dielectric stack and a mandrel layer positioned on the dielectric stack;

patterning an array of sacrificial mandrel features into the mandrel layer and on top of an insulating layer of the dielectric stack;

forming spacer elements located adjacent each of the sacrificial mandrel features;

forming a self-aligned non-mandrel cut adjacent to one of the spacer elements adjacent to one of the sacrificial mandrel features,

filling the self-aligned non-mandrel cut with a first placeholder material, wherein a top surface of the first placeholder material is substantially uniform with a top surface of the adjacent spacer element;

removing the sacrificial mandrel features, wherein removal of the sacrificial mandrel features creates a plurality of trenches located between spacer elements;

forming one or more self-aligned mandrel cuts in one or more of the plurality of trenches after removal of the sacrificial mandrel features,

filling the self-aligned mandrel with a second placeholder material, wherein the second placeholder material contacts adjacent spacer elements, wherein a top surface of the second placeholder material is substantially uniform with a top surface of the adjacent spacer elements;

forming non-mandrel openings on top of the insulating layer;

etching continuity line openings into the dielectric stack, wherein the self-aligned non-mandrel cut is disposed to interrupt a first of the continuity line openings and the one or more self-aligned mandrel cut cuts are disposed to interrupt a second of the continuity line openings; and

forming metal lines in the continuity line openings, except where the self-aligned non-mandrel cut and the one or more self-aligned mandrel cuts are disposed.

2 . The method of claim 1 , further comprising removing the mandrel spacers prior to etching the continuity line openings.

3 . The method of claim 1 , wherein a thickness of the mandrel spacers on the sidewalls of the sacrificial mandrel features is evenly formed.

4 . The method of claim 1 , wherein the forming non-mandrel openings includes removing the first placeholder material and the second placeholder material.

5 . The method of claim 1 , further comprising forming a flowable silicon dioxide layer adjacent to the spacer elements and the self-aligned non-mandrel cut.

6 . The method of claim 5 , further comprising removing the flowable silicon dioxide layer, forming one or more of the continuity line openings.

7 . A method of fabricating a semiconductor device, comprising:

providing a semiconductor structure having a dielectric stack, an interconnect layer in the dielectric stack, and a mandrel layer positioned on the dielectric stack;

patterning an array of mandrels into the mandrel layer and on top of an insulating layer of the dielectric stack;

forming spacer elements located adjacent each of the mandrels;

forming a self-aligned non-mandrel cut adjacent to one of the spacer elements adjacent to one of the mandrels,

filling the self-aligned non-mandrel cut with a first placeholder material, wherein a top surface of the first placeholder material is substantially uniform with a top surface of the adjacent spacer element;

removing the mandrels, wherein removal of the mandrels creates a plurality of parallel trenches;

forming a self-aligned mandrel cut in one of the plurality of parallel trenches, filling the self-aligned mandrel cut with a second placeholder material, wherein the second placeholder material contacts adjacent spacer elements, wherein a top surface of the second placeholder material is substantially uniform with a top surface of the adjacent spacer elements;

forming non-mandrel openings on top of the insulating layer, wherein the non-mandrel openings are parallel to the plurality of parallel trenches;

forming continuity lines in the interconnect layer, wherein:

the continuity lines are formed in the plurality of parallel trenches and in the non-mandrel openings;

a first continuity line of the continuity lines includes the self-aligned non-mandrel cut; and

a second continuity line of the continuity lines includes the self-aligned mandrel cut.

8 . The method of claim 7 , wherein an end of the first continuity line is staggered from an end of the second continuity line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2023
From: YANG, XIAOMING; CLEVENGER, LAWRENCE A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 063103/0210 →
Continuity (1)
Related Publication 20240321587A1 · Sep 26, 2024
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