Spacer-defined process for lithography-etch double patterning for interconnects
One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.
1. A semiconductor device, comprising:
a substrate having a first pattern; and
a layer formed on the substrate and comprising an ultra-low-k dielectric film having a second pattern, wherein the second pattern comprises one or more open regions causing the first pattern of the substrate to be visible through the one or more open, unfilled regions, wherein a first one of the one or more open regions of the second pattern is wholly enclosed in an interior area of the layer, and wherein a second one of the one or more open regions of the second pattern comprises spacer material separating an interior region of the second one of the one or more open regions into at least two portions.
2. The semiconductor device of claim 1 , wherein the first pattern is orthogonal to the second pattern.
3. The semiconductor device of claim 1 , wherein the second pattern has a thickness 40-150 nanometers (nm).
4. The semiconductor device of claim 1 , wherein the substrate is composed of copper.
5. The semiconductor device of claim 1 , wherein the at least one of the one or more open regions of the second pattern is wholly enclosed in an interior area of the layer that is non-contiguous with an outer edge of the layer.
6. The semiconductor device of claim 1 , wherein the k of the ultra-low-k dielectric material is 2.0-4.0.
7. The semiconductor device of claim 1 , wherein the substrate is a bottom layer of the semiconductor device and wherein the layer is a top layer of the semiconductor device.
8. The semiconductor of claim 1 , wherein the first one of the one or more open regions of the second pattern is a single uninterrupted open region and wherein the second one of the one or more open regions is distinct from the first one of the one or more open regions.