Stacked FET vertical diode
View Patent ↗A semiconductor structure including a stacked FET vertical diode is provided. The stacked FET vertical diode includes vertically stacked source/drain regions of opposite conductivity that are electrically connected by a semiconductor material layer that is positioned between the vertically stacked source/drain regions.
1 . A semiconductor structure comprising:
a stacked field effect transistor (FET) vertical diode located in a diode region of a semiconductor substrate, wherein the stacked FET vertical diode comprises a first FET having first conductivity type source/drain regions, a second FET located above the first FET and having second conductivity type source/drain regions that are of an opposite conductivity than the first conductivity type source/drain regions, and a semiconductor material layer electrically connecting the first conductivity type source/drain regions of the first FET with the second conductivity type source/drain regions of the second FET.
2 . The semiconductor structure of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
3 . The semiconductor structure of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.
4 . The semiconductor structure of claim 1 , wherein the semiconductor material layer is an intrinsic semiconductor material.
5 . The semiconductor structure of claim 1 , wherein the semiconductor material layer is a doped semiconductor material having a dopant concentration of 5e18 atoms/cm 3 or less.
6 . The semiconductor structure of claim 5 , wherein the doped semiconductor material comprises a p-type dopant.
7 . The semiconductor structure of claim 5 , wherein the doped semiconductor material comprises an-type dopant.
8 . The semiconductor structure of claim 1 , wherein the semiconductor material layer is a polycrystalline semiconductor material.
9 . The semiconductor structure of claim 8 , wherein the polycrystalline semiconductor material is polycrystalline silicon.
10 . The semiconductor structure of claim 1 , further comprising a first semiconductor channel material region located laterally between each of the first conductivity type source/drain regions, and a second semiconductor channel material region located laterally between each of the second conductivity type source/drain regions.
11 . The semiconductor structure of claim 10 , wherein the first FET comprises a first gate dielectric material layer located on the first semiconductor channel material region and a first gate electrode located on the first gate dielectric material layer, and the second FET comprises a second gate dielectric material layer located on the second semiconductor channel material region and a second gate electrode located on the second gate dielectric material layer.
12 . The semiconductor structure of claim 11 , further comprising a first gate spacer located on the first gate dielectric material layer and contacting a sidewall of the first gate electrode, and a second gate spacer located on the second gate dielectric material layer and contacting a sidewall of the second gate electrode.
13 . The semiconductor structure of claim 12 , wherein the first gate spacer further contacts the semiconductor material layer.
14 . The semiconductor structure of claim 1 , wherein the semiconductor substrate comprises an insulator layer located on a base semiconductor material layer, and the insulator layer contacts each of the first conductivity type source/drain regions.
15 . The semiconductor structure of claim 1 , wherein the semiconductor substrate comprises a base semiconductor material layer, and the base semiconductor material layer contacts each of the first conductivity type source/drain regions.
16 . The semiconductor structure of claim 1 , further comprising a stacked FET located in a stacked FET device region of the semiconductor substrate, wherein the stacked FET device region is located adjacent to the diode region of the semiconductor substrate.
17 . The semiconductor structure of claim 16 , wherein the stacked FET comprises a third FET having third conductivity type source/drain regions, a fourth FET located above the third FET and having fourth conductivity type source/drain regions, and a dielectric material layer electrically insulating the third conductivity type source/drain regions of the third FET from the fourth conductivity type source/drain regions of the fourth FET.
18 . The semiconductor structure of claim 17 , wherein the dielectric material layer comprises silicon dioxide, silicon nitride, silicon oxynitride or any combination thereof.
19 . The semiconductor structure of claim 17 , wherein the third conductivity type is n-type and the fourth conductivity type is p-type.
20 . The semiconductor structure of claim 17 , wherein the third conductivity type is p-type and the fourth conductivity type is n-type.