Nanosheet substrate isolated source/drain epitaxy via airgap
Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.
1. A semiconductor structure comprising:
a plurality of stacked and suspended semiconductor channel material nanosheets located above a horizontal planar surface of a semiconductor substrate;
a functional gate structure surrounding a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets;
a source/drain (S/D) region on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets; and
an airgap located between the source/drain (S/D) region and a recessed surface of the semiconductor substrate, wherein the airgap entirely separates the source/drain (S/D) region from the recessed surface of the semiconductor substrate, and the airgap has a first surface that directly contacts a portion of the horizontal planar surface of the semiconductor substrate.
2. The semiconductor structure of claim 1 , further comprising an inner gate spacer contacting a sidewall of the functional gate structure and located on an outer portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets.
3. The semiconductor structure of claim 1 , wherein each source/drain (S/D) region has a faceted upper surface.
4. The semiconductor structure of claim 1 , further comprising an interlevel dielectric (ILD) material located above each S/D region.
5. The semiconductor structure of claim 4 , wherein the ILD material atop each S/D region has a topmost surface that is coplanar with a topmost surface of the functional gate structure.
6. The semiconductor structure of claim 1 , wherein sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets are vertically aligned to each other.
7. The semiconductor structure of claim 1 , wherein the airgap has a second surface that directly contacts the recessed surface of the semiconductor substrate.
8. The semiconductor structure of claim 1 , wherein the recessed surface of the semiconductor substrate is a concave surface.
9. The semiconductor structure of claim 2 , wherein the airgap contacts a sidewall of a bottommost inner spacer.
10. The semiconductor structure of claim 1 , wherein the airgap has a topmost surface that does not extend beyond a bottommost surface of a bottommost semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets.
11. The semiconductor structure of claim 1 , wherein no parasitic transistor is present beneath the plurality of stacked and suspended semiconductor channel material nanosheets.