Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
View Patent ↗A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier. The conducting material less-than-fills the void-space in the lowest first tier. The conducting material is etched from the lowest first tier. After the etching of the conducting material, conductive material is deposited into the void-space of the lowest first tier and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Additional embodiments, including structure independent of method, are disclosed.
1. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, conducting material of a lowest of the one of the conductive tiers being directly against the conductor material of the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier; and
the conducting material in the lowest conductive the one conductive tier being directly against a sidewall of the channel material of individual of the channel-material strings.
2. The memory array of claim 1 wherein at least an uppermost portion of the conductor material of the conductor tier is of the same composition as the conducting material of the lowest conductive the one conductive that is there-against.
3. The memory array of claim 1 wherein at least an uppermost portion of the conductor material of the conductor tier is of different same composition as the conducting material of the lowest conductive the one conductive tier that is there-against.
4. The memory array of claim 1 wherein the lowest conductive the one conductive tier is thicker than the conductive tiers there-above.
5. The memory array of claim 4 wherein the lowest conductive the one conductive tier is at least 1.5 times thicker than the conductive tiers there-above.
6. The memory array of claim 1 wherein a lowest surface of the channel material of the channel-material strings is not directly against the conductor material of the conductor tier.
7. The memory array of claim 1 wherein the conducting material in the lowest conductive the one conductive tier is directly against an uppermost surface of the conductor material of the conductor tier.
8. The memory array of claim 1 comprising NAND.
9. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, conducting material of a lowest of the one of the conductive tiers being directly against the conductor material of the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
intervening material laterally-between immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier;
the conducting material in the lowest conductive the one conductive tier being directly electrically coupled to the channel material of individual of the channel-material strings; and
the conducting material of the conductive tiers that are above the lowest conductive the one conductive tier projecting laterally in a direction away from the channel-material strings into the insulating material of the intervening material.
10. The memory array of claim 9 wherein the conducting material in the lowest conductive the one conductive tier is directly against a sidewall of the channel material of the individual channel-material strings.
11. The memory array of claim 9 wherein the lowest conductive the one conductive tier is at least 1.5 times thicker than the conductive tiers there-above.
12. The memory array of claim 9 wherein a lowest surface of the channel material of the channel-material strings is not directly against the conductor material of the conductor tier.
13. The memory array of claim 9 wherein the insulating material of the intervening material projects laterally in a direction towards the channel-material strings to be directly under a lowest of the insulative tiers.
14. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, conducting material of a lowest of the one of the conductive tiers being directly against the conductor material of the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
intervening material laterally-between immediately-laterally-adjacent of memory blocks, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier;
the conducting material in the lowest conductive the one conductive tier being directly electrically coupled to the channel material of individual of the channel-material strings; and
the insulating material of the intervening material projecting laterally in a direction towards the channel-material strings to be directly under a lowest of the insulative tiers.
15. The memory array of claim 14 wherein the conducting material in the lowest conductive the one conductive tier is directly against a sidewall of the channel material of the individual channel-material strings.
16. The memory array of claim 14 wherein the lowest conductive the one conductive tier is at least 1.5 times thicker than the conductive tiers there-above.
17. The memory array of claim 14 wherein a lowest surface of the channel material of the channel-material strings is not directly against the conductor material of the conductor tier.