Active bridge chiplet with integrated cache
A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.
1 . A processor comprising:
a chiplet array including a first chiplet, a second chiplet, and an active bridge chiplet shared by the first chiplet and the second chiplet, the active bridge chiplet configured to actively route inter-chiplet memory access requests and comprising memory shared by the first chiplet and the second chiplet,
wherein the first chiplet is configured to:
route one or more memory access requests serviceable by the active bridge chiplet or the second chiplet to the active bridge chiplet or the second chiplet for servicing.
2 . The processor of claim 1 , wherein the first chiplet is configured to receive a memory access request from a processor.
3 . The processor of claim 2 , wherein the first chiplet is further configured to
return data associated with the memory access request to the processor.
4 . The processor of claim 2 , wherein the first chiplet further comprises a scalable data fabric configured to receive the memory access request from the processor.
5 . The processor of claim 1 , wherein the first chiplet is configured to route a memory access request by routing the memory access request to the second chiplet via the active bridge chiplet.
6 . The processor of claim 5 , wherein the first chiplet is configured to route the memory access request to the second chiplet in response to data associated with the memory access request being stored in a memory associated with the second chiplet.
7 . The processor of claim 1 , wherein the first chiplet is configured to route a memory access request by routing the memory access request to the memory at the active bridge chiplet.
8 . The processor of claim 7 , wherein the memory comprises a unified cache memory that is coherent across the first chiplet and the second chiplet.
9 . The processor of claim 1 , wherein the first chiplet is configured to request data, associated with a memory access request, from the active bridge chiplet.
10 . The processor of claim 1 , wherein the active bridge chiplet communicably couples chiplets in the chiplet array.
11 . A system comprising:
a processor communicably coupled to a first chiplet of a chiplet array, wherein the chiplet array includes:
an active bridge chiplet configured to actively route inter-chiplet memory access requests and having memory shared by the first chiplet and a second chiplet;
the first chiplet communicably coupled to the processor via a bus; and
a second chiplet communicably coupled to the first chiplet via the active bridge chiplet,
wherein the first chiplet is configured to route one or more memory access requests serviceable by the active bridge chiplet or the second chiplet to the active bridge chiplet or the second chiplet for servicing.
12 . The system of claim 11 , wherein the first chiplet is further configured to:
responsive to data associated with a memory access request received from the processor being locally cached at memory coherent only within the first chiplet, service the memory access request.
13 . The system of claim 11 , wherein the first chiplet is further configured to:
responsive to data associated with a memory access request received from the processor being cached at a level of cache memory that is shared by the first chiplet and the second chiplet, route the memory access request to the active bridge chiplet for servicing.
14 . The system of claim 11 , wherein the first chiplet is further configured to:
responsive to data associated with a memory access request received from the processor being stored in a memory associated with the second chiplet, route the memory access request to the second chiplet via the active bridge chiplet for servicing.
15 . A method comprising:
receiving, at a first chiplet of a chiplet array, a memory access request from a processor;
responsive to the memory access request being serviceable by a second chiplet of the chiplet array, routing, by an active bridge chiplet controller of the first chiplet, the memory access request to the second chiplet for servicing;
responsive to the memory access request being serviceable by an active bridge chiplet having memory shared by the first chiplet and the second chiplet, routing, by the active bridge chiplet controller of the first chiplet, the memory access request to the memory at the active bridge chiplet that is shared by the first chiplet and the second chiplet for servicing; and
returning data associated with the memory access request to the processor.
16 . The method of claim 15 , wherein routing the memory access request to the second chiplet is in response to data associated with the memory access request being stored in a memory associated with the second chiplet.
17 . The method of claim 15 , wherein routing the memory access request comprises:
routing the memory access request to the second chiplet via the active bridge chiplet.
18 . The method of claim 15 , wherein the memory is a unified last level cache at the active bridge chiplet.