Semiconductor device and method of manufacturing the same
A semiconductor device includes active patterns on a substrate, source/drain patterns, first and second separation structures, wherein adjacent source/drain patterns are interposed between the first and second separation structures, an interlayer insulating layer on the source/drain patterns and first and second separation structures, a through-via between the adjacent source/drain patterns, penetrating the interlayer insulating layer, and extending toward the substrate, wherein a top of the through-via is coplanar with a top of the interlayer insulating layer, a dielectric layer selectively on the top of the interlayer insulating layer, and opening the top of the through-via, a power via guided to connect to the top of the through-via by the dielectric layer, a power line on the power via and electrically connected to the through-via through the power via, a power delivery network layer on a bottom of the substrate, and a lower conductor under the through-via.
1 . A semiconductor device comprising:
active patterns adjacent to each other on a substrate;
source/drain patterns adjacent to each other on the active patterns, respectively;
a first separation structure and a second separation structure crossing the active patterns, wherein the source/drain patterns that are adjacent to each other are interposed between the first and second separation structures;
an interlayer insulating layer on the source/drain patterns and the first and second separation structures;
a through-via between a first source/drain pattern of the source/drain patterns and a second source/drain pattern of the source/drain patterns adjacent to the first source/drain pattern, the through-via penetrating through the interlayer insulating layer and extending toward the substrate, wherein a top surface of the through-via is coplanar with a top surface of the interlayer insulating layer;
a dielectric layer selectively provided on the top surface of the interlayer insulating layer, the dielectric layer having an opening exposing the top surface of the through-via;
a power via extending through the opening of the dielectric layer to connect to the top surface of the through-via, wherein the dielectric layer is configured to guide the power via to the top surface of the through-via;
a power line provided on the power via, the power line being electrically connected to the through-via through the power via;
a power delivery network layer on a bottom surface of the substrate; and
a lower conductor between the power delivery network layer and the through-via.
2 . The semiconductor device as claimed in claim 1 , wherein a width of the power via is greater than a width of the through-via.
3 . The semiconductor device as claimed in claim 1 , wherein the power via is in contact with at least a portion of the dielectric layer.
4 . The semiconductor device as claimed in claim 1 , further comprising:
an active contact electrically connected to at least one of the active patterns; and
a first via between the active contact and the power line,
wherein the dielectric layer is configured to guide the first via to connect to a top surface of the active contact.
5 . The semiconductor device as claimed in claim 1 , further comprising:
an active contact electrically connected to at least one of the active patterns; and
a first via between the active contact and the power line,
wherein the first via and the power via are connected to each other to form one large via, and
wherein the large via is spaced apart from the interlayer insulating layer by the dielectric layer.
6 . The semiconductor device as claimed in claim 1 , further comprising an etch stop layer on the dielectric layer,
wherein the power via passes through the etch stop layer and is in contact with the top surface of the through-via.
7 . The semiconductor device as claimed in claim 1 , wherein the power delivery network layer is configured to apply a source voltage or a drain voltage to the power line.
8 . The semiconductor device as claimed in claim 1 , wherein the lower conductor vertically overlaps the power line, and
wherein the lower conductor has a line shape or a contact shape.
9 . The semiconductor device as claimed in claim 1 , wherein a width of the through-via decreases as the through-via approaches the bottom surface of the substrate, and
wherein a width of the lower conductor increases as the lower conductor approaches the bottom surface of the substrate.
10 . The semiconductor device as claimed in claim 1 , wherein the through-via is interposed between the first and second separation structures.
11 . A semiconductor device comprising:
a plurality of power lines on a substrate, the plurality of power lines being arranged in a first direction and parallel to each other in a second direction;
a plurality of logic cells two-dimensionally arranged on the substrate;
a plurality of tap cells arranged on the substrate in the first direction; and
a power delivery network layer below the substrate,
wherein each of the plurality of tap cells includes:
a lower conductor buried in a lower portion of the substrate, the lower conductor electrically connected to the power delivery network layer;
a through-via passing through an interlayer insulating layer and connected to the lower conductor;
a dielectric layer selectively provided on a top surface of the interlayer insulating layer, the dielectric layer having an opening exposing a top surface of the through-via; and
a power via electrically connecting the through-via to a corresponding one of the power lines,
wherein the power via is in direct contact with the top surface of the through-via, and
wherein a width of the power via is greater than a width of the through-via.
12 . The semiconductor device as claimed in claim 11 , wherein the power via is spaced apart from the interlayer insulating layer by the dielectric layer.
13 . The semiconductor device as claimed in claim 11 , wherein each of the plurality of tap cells further includes a first separation structure on a first boundary of a respective tap cell and a second separation structure on a second boundary of the respective tap cell.
14 . The semiconductor device as claimed in claim 11 , wherein each of the plurality of tap cells further includes an etch stop layer on the dielectric layer, and
wherein the power via passes through the etch stop layer and is in contact with the top surface of the through-via.
15 . The semiconductor device as claimed in claim 11 , wherein the power delivery network layer is configured to apply a source voltage or a drain voltage to each power line of the plurality of power lines.
16 . A semiconductor device comprising:
a first power line and a second power line on a substrate, the first and second power lines being spaced apart from each other in a first direction and extending parallel to each other in a second direction;
a logic cell and a tap cell that are between the first and second power lines, the logic cell and the tap cell being adjacent to each other in the second direction;
a first active pattern and a second active pattern on the logic cell, the first and second active patterns being spaced apart from each other in the first direction;
a first channel pattern and a first source/drain pattern on the first active pattern;
a second channel pattern and a second source/drain pattern on the second active pattern, the second source/drain pattern having a conductivity type different from that of the first source/drain pattern;
an interlayer insulating layer on the first and second source/drain patterns;
a first active contact and a second active contact electrically connected to the first and second source/drain patterns, respectively, through the interlayer insulating layer;
a first through-via and a second through-via on the tap cell, the first and second through-vias passing through the interlayer insulating layer and extending toward the substrate;
a dielectric layer selectively provided on a top surface of the interlayer insulating layer, the dielectric layer having openings exposing top surfaces of the first and second through-vias and top surfaces of the first and second active contacts;
a first power via contacting the top surface of the first through-via exposed by the openings in the dielectric layer, the first power via electrically connecting the first through-via to the first power line;
a second power via contacting the top surface of the second through-via exposed by the openings in the dielectric layer, the second power via electrically connecting the second through-via to the second power line;
a first via in contact with the top surface of the first active contact exposed by the openings in the dielectric layer, the first via electrically connecting the first active contact to the first power line;
a second via in contact with the top surface of the second active contact exposed by the openings in the dielectric layer, the second via electrically connecting the second active contact to the second power line;
a power delivery network layer provided on a bottom surface of the substrate; and
a first lower conductor and a second lower conductor respectively provided between the power delivery network layer and the first and second through-vias.
17 . The semiconductor device as claimed in claim 16 , further including a first separation structure provided on a first boundary of the tap cell and a second separation structure provided on a second boundary of the tap cell, wherein first and second boundaries face each other in the second direction,
wherein each of the first and second through-vias is interposed between the first and second separation structures.
18 . The semiconductor device as claimed in claim 16 , further including:
a gate electrode on the first and second channel patterns;
a gate insulating layer interposed between the gate electrode and the first and second channel patterns;
a gate spacer on a sidewall of the gate electrode;
a gate capping pattern on a top surface of the gate electrode; and
a gate contact electrically connected to the gate electrode through the interlayer insulating layer and the gate capping pattern.
19 . The semiconductor device as claimed in claim 16 , wherein the power delivery network layer is configured to apply a source voltage to one of the first and second power lines, and
wherein the power delivery network layer is configured to apply a drain voltage to the other one of the first and second power lines.
20 . The semiconductor device as claimed in claim 16 , wherein a width of the first power via is greater than a width of the first through-via, and
wherein a width of the second power via is greater than a width of the second through-via.