Semiconductor device and stack of semiconductor chips
A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.
1. A semiconductor device, comprising:
a substrate including a logic cell region and a connection region;
a dummy transistor on the connection region;
an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor;
a first metal layer on the intermediate connection layer;
an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern; and
a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region,
wherein an upper portion of the penetration contact protrudes above the etch stop layer,
the first metal layer including a first interconnection line, a second interconnection line, and a via below the second interconnection line,
the via penetrates the etch stop layer and connects the second interconnection line to the connection pattern, and
a top surface of the penetration contact is in direct contact with a bottom surface of the first interconnection line.
2. The semiconductor device of claim 1 , wherein
a top surface of the via is in direct contact with a bottom surface of the second interconnection line, and
the lowermost level of the bottom surface of the first interconnection line is lower than the lowermost level of the bottom surface of the second interconnection line.
3. The semiconductor device of claim 2 , wherein
the top surface of the penetration contact includes a concave recess, and
the bottom surface of the first interconnection line has a convex profile corresponding to the top surface of the penetration contact.
4. The semiconductor device of claim 1 , further comprising a protection insulating pattern on the etch stop layer covering the upper portion of the penetration contact,
wherein
a side surface of the upper portion of the penetration contact includes a first upper side surface and a second upper side surface on the first upper side surface,
the etch stop layer covers the first upper side surface, and
the protection insulating pattern covers the second upper side surface.
5. The semiconductor device of claim 4 , wherein the protection insulating pattern is vertically extended from a top surface of the etch stop layer to the bottom surface of the first interconnection line along the second upper side surface.
6. The semiconductor device of claim 4 , wherein the protection insulating pattern partially covers a top surface the etch stop layer adjacent to the penetration contact.
7. The semiconductor device of claim 1 , wherein a bottom surface of the etch stop layer is coplanar with a bottom surface of the via.
8. The semiconductor device of claim 1 , further comprising a logic transistor on the logic cell region,
wherein the logic transistor and the dummy transistor are each a three-dimensional field effect transistor.
9. The semiconductor device of claim 1 , wherein the dummy transistor includes an active pattern on the connection region;
a device isolation layer filling a trench, which bisects the active pattern;
a gate electrode crossing the active pattern; and
a source/drain pattern adjacent to a side of the gate electrode,
wherein the penetration contact penetrates the device isolation layer.
10. The semiconductor device of claim 1 , wherein the penetration contact includes
a pillar shaped conductive pattern;
a barrier pattern enclosing an outer side surface of the conductive pattern; and
an insulating spacer enclosing an outer side surface of the barrier pattern.
11. A semiconductor device, comprising:
a substrate including a logic cell region and a connection region;
a dummy transistor on the connection region;
an intermediate connection layer on the dummy transistor;
a first metal layer on the intermediate connection layer;
an etch stop layer between the intermediate connection layer and the first metal layer; and
a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region,
wherein an upper portion of the penetration contact protrudes above the etch stop layer,
the first metal layer includes a first interconnection line, a second interconnection line, and a via below the second interconnection line,
the via penetrates the etch stop layer and connects the second interconnection line to the intermediate connection layer,
a top surface of the penetration contact is in direct contact with a bottom surface of the first interconnection line,
a top surface of the via is in direct contact with a bottom surface of the second interconnection line, and
the lowermost level of the bottom surface of the first interconnection line is lower than the lowermost level of the bottom surface of the second interconnection line.
12. The semiconductor device of claim 11 , wherein the top surface of the penetration contact includes a concave recess, and
the bottom surface of the first interconnection line has a convex profile corresponding to the top surface of the penetration contact.
13. The semiconductor device of claim 11 , further comprising a protection insulating pattern on the etch stop layer covering the upper portion of the penetration contact,
wherein
a side surface of the upper portion of the penetration contact includes a first upper side surface and a second upper side surface on the first upper side surface,
the etch stop layer covers the first upper side surface, and
the protection insulating pattern covers the second upper side surface.
14. The semiconductor device of claim 13 , wherein the protection insulating pattern is vertically extended from a top surface of the etch stop layer to the bottom surface of the first interconnection line along the second upper side surface.
15. The semiconductor device of claim 11 , wherein the intermediate connection layer includes
an active contact electrically connected to a source/drain pattern of the dummy transistor; and
a gate contact electrically connected to a gate electrode of the dummy transistor.
16. A semiconductor device, comprising:
a substrate including a logic cell region and a connection region;
an active pattern on each of the logic cell region and the connection region;
a device isolation layer covering a lower side surface of the active pattern, an upper portion of the active pattern protruding above the device isolation layer;
a gate electrode crossing the active pattern;
a source/drain pattern adjacent to a side of the gate electrode, the source/drain pattern filling a recess in the upper portion of the active pattern;
an intermediate connection layer on the gate electrode and the source/drain pattern, the intermediate connection layer including an active contact electrically connected to the source/drain pattern and a gate contact electrically connected to the gate electrode;
a first metal layer on the intermediate connection layer, the first metal layer including a first interconnection line, a second interconnection line, and a via electrically connecting the second interconnection line to the intermediate connection layer;
an etch stop layer between the intermediate connection layer and the first metal layer;
a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region, an upper portion of the penetration contact protruding above the etch stop layer; and
a protection insulating pattern on the etch stop layer covering the upper portion of the penetration contact,
wherein a side surface of the upper portion of the penetration contact includes a first upper side surface and a second upper side surface on the first upper side surface,
the etch stop layer covers the first upper side surface,
the protection insulating pattern covers the second upper side surface, and
a top surface of the penetration contact is in direct contact with a bottom surface of the first interconnection line.
17. The semiconductor device of claim 16 , wherein
a top surface of the via is in direct contact with a bottom surface of the second interconnection line, and
the lowermost level of the bottom surface of the first interconnection line is lower than the lowermost level of the bottom surface of the second interconnection line.
18. The semiconductor device of claim 16 , wherein the protection insulating pattern is vertically extended from a top surface of the etch stop layer to the bottom surface of the first interconnection line along the second upper side surface.
19. The semiconductor device of claim 16 , wherein the protection insulating pattern partially covers a top surface of the etch stop layer adjacent to the penetration contact.
20. The semiconductor device of claim 16 , wherein the penetration contact penetrates the device isolation layer on the connection region.