Low density parity check decoder
A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
1. A method for decoding a low density parity check (LDPC) code, comprising:
selecting a first R message from a plurality of possible R messages based on a message index value and a sign bit;
delaying a Q message in a memory until an R select unit provides a second R message;
summing the second R message and the delayed Q message to produce a P message; and
permuting the P message by a difference of a permutation of a block currently being processed and a permutation of a block previously processed,
wherein the block currently being processed and the block previously processed are in a same block column.
2. The method of claim 1 , further comprising generating the second R message based on a permuted Q message and a sign bit from a Q message.
3. The method of claim 1 , further comprising storing sign bits for a plurality of LDPC parity check matrix layers in an array of sign bit memory banks, wherein each memory bank stores sign bits for a layer of the matrix.
4. The method of claim 1 , further comprising subtracting the first R message from a permuted P message to produce a Q message that is provided to a check node unit (CNU).
5. The method of claim 1 , further comprising permuting the P message by a combination of permutation by a permuter and memory addressing.
6. The method of claim 1 , further comprising selecting one of a channel log-likelihood ratio (LLR) value and a P message to input to a permuter, wherein the LLR value is selected to initialize decoding.
7. The method of claim 1 , further comprising selecting one of a channel log-likelihood ratio (LLR) value and a Q message to input to the memory, wherein the LLR value is selected to initialize decoding.
8. A low density parity check (LDPC) code decoder, comprising:
decoding circuitry configured to process blocks of an LDPC matrix, the decoding circuitry comprising:
a control unit that controls processing by the decoding circuitry, the control unit configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order, wherein the control unit is configured to cause the decoding circuitry to process each block of the LDPC matrix in processing substeps comprising:
a first R message update substep that provides a first R message, wherein the first R message is produced for a block of a different layer of the matrix from a layer containing a block currently being processed;
a second R message update substep that provides a second R message, wherein the second R message is produced for a layer of the matrix currently being processed;
a P message substep that generates updated P messages;
a Q message substep that computes variable node messages (Q messages); and
a check node partial state processing substep that updates partial state of the layer based on Q messages computed for the block.
9. The LDPC code decoder of claim 8 , wherein the decoding circuitry is configured to generate a Q message by combining the second R message with a P message.
10. The LDPC code decoder of claim 8 , wherein the decoding circuitry further comprises a permuter configured to permute a P message.
11. The LDPC code decoder of claim 10 , wherein the permuter is configured to permute the P message by a difference of a permutation of a second block currently being processed and a permutation of a block previously processed, wherein the second block currently being processed and the block previously processed are in a same block column of the LDPC matrix.
12. The LDPC code decoder of claim 8 , wherein the decoding circuitry is configured to subtract a second R message from a permuted P message to generate a Q message.
13. The LDPC code decoder of claim 8 , wherein the decoding circuitry is configured to select one of an updated P message and a channel log-likelihood ratio (LLR) value for storage in a P memory, wherein the channel LLR value is selected to initialize decoding.
14. The LDPC code decoder of claim 8 , wherein the decoding circuitry is further configured to select an R message from a plurality of previously generated possible R messages based on a message index value and a sign bit.
15. The LDPC code decoder of claim 8 , wherein the LDPC matrix is quasi-cyclic.
16. A method, comprising:
processing blocks of a layer of a low density parity check (LDPC) matrix out of order, wherein processing each of the blocks comprises:
providing a first R message, wherein the first R message is produced for a block of a different layer of the LDPC matrix from a layer containing a block currently being processed;
providing a second R message, wherein the second R message is produced for a layer of the matrix currently being processed;
generating updated P messages;
computing variable node messages (Q messages); and
updating partial state of the layer based on Q messages computed for the block.
17. The method of claim 16 , further comprising generating a Q message by combining the second R message with a P message.
18. The method of claim 16 , further comprising permuting a P message.
19. The method of claim 18 , wherein permuting the P message comprising permuting the P message by a difference of a permutation of a second block currently being processed and a permutation of a block previously processed, wherein the second block currently being processed and the block previously processed are in a same block column of the LDPC matrix.
20. The method of claim 16 , further comprising generating a Q message by subtracting the second R message from a permuted P message.
21. The method of claim 16 , further comprising:
selecting one of an updated P message and a channel log-likelihood ratio (LLR) value for storage in a P memory; and
selecting a channel LLR value to initialize decoding.
22. The method of claim 16 , further comprising selecting an R message from a plurality of previously generated possible R messages based on a message index value and a sign bit.
23. The method of claim 16 , wherein the LDPC matrix is quasi-cyclic.
24. A low density parity check (LDPC) code decoder, comprising:
a control unit that controls decoder processing, wherein the control unit is configured to cause the decoder to:
process blocks of an LDPC matrix out of order; and
process each block of the matrix in processing substeps comprising:
a first R message update substep that produces a first R message for a block of a different layer of the matrix from a layer containing a block currently being processed;
a second R message update substep that selects a second R message for a layer of the matrix currently being processed;
a P message substep that generates updated P messages; and
a Q message substep that computes variable node messages (Q messages); and
a first permuter configured to permute a P message,
wherein the permuter permutes the P message by the difference of a permutation of a block currently being processed and a permutation of a block previously processed, and
wherein the block currently being processed and the block previously processed are in a same block column.
25. The LDPC code decoder of claim 24 , further comprising:
a P message generator configured to combine the first R message with a Q message to produce a P message; and
a Q message generator configured to combine the second R message with a P message to produce a Q message.
26. The LDPC code decoder of claim 24 , further comprising a Q message memory that stores a Q message that is to be combined with an R message to produce a P message.
27. The LDPC code decoder of claim 24 , further comprising a P message memory that stores a P message that is to be combined with the first R message to produce a Q message.
28. The LDPC code decoder of claim 24 , wherein the control unit is configured to cause the decoder to generate an updated P message based on a determination of a final state for a block row.
29. A method for decoding a low density parity check (LDPC) code, comprising:
processing blocks of an LDPC matrix out of order;
processing each block of the LDPC matrix in processing substeps that comprise:
a first R message update substep that produces a first R new message for a block of a different layer of the matrix from a layer containing a block currently being processed;
a second R message update substep that selects a second R message for a layer of the matrix currently being processed;
a P message substep that generates updated P messages; and
a Q message substep that computes variable node messages (Q messages); and
permuting a P message,
wherein the permuting comprises permuting the P message by the difference of the permutation of a block currently being processed and the permutation of a block previously processed, and
wherein the block currently being processed and the block previously processed are in a same block column.
30. The method of claim 29 , further comprising:
combining the first R message with a Q message to produce a P message; and
combining the second R message with a P message to produce a Q message.
31. The method of claim 29 , further comprising storing a Q message that is to be combined with an R message to produce a P message.
32. The method of claim 29 , further comprising storing a P message that is to be combined with the second R message to produce a Q message.
33. The method of claim 29 , wherein generation of the updated P message comprises generating the updated P message based on a determination of a final state for a block row.
34. A low density parity check (LDPC) code decoder, comprising:
an array of reconfigurable minimum finder units configured to:
perform block parallel processing of an LDPC matrix;
selectably process in parallel a first plurality (dc1) of block columns of a plurality (M1) of rows of a layer of a first LDPC matrix, where:
dc1 is a check node degree of a block row of the first LDPC matrix;
p1 is a total number of rows of the block row of a first LDPC matrix; and
M1<=p1; and
selectably process in parallel a second plurality (dc2) of block columns of a plurality (M2) of rows of a layer of a second LDPC matrix, where:
dc2 is a check node degree of a block row of the second LDPC matrix, and dcl is different from dc2;
p2 is a total number of rows of the block row of the second LDPC matrix;
M2<=p2; and
M2 is different from M1.
35. The LDPC code decoder of claim 34 , wherein the array of reconfigurable minimum finder units is configured to:
partition a vector of input values into a plurality of sub-vectors;
determine a first minimum value and a second minimum value for each sub-vector; and
determine a first minimum and a second minimum of the vector based on the first minimum value and second minimum value of the sub-vectors.