Wafer level proximity sensor and method of making same
Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.
1 . A method, comprising:
at each integrated circuit area of a plurality of integrated circuit areas for a silicon integrated circuit substrate wafer, forming at least one photosensitive region and at least one front connection pad;
forming a plurality of first trenches and a plurality of second trenches in a silicon cap wafer;
providing an opaque light barrier at the silicon cap wafer to block light transmission through the silicon cap wafer between the first and second trenches;
wafer-to-wafer bonding of the silicon cap wafer to the silicon integrated circuit substrate wafer to form a bonded wafer sandwich, where an opening of each first trench in the silicon cap wafer faces a corresponding photosensitive region of the silicon integrated circuit substrate wafer and wherein an opening of each second trench in the silicon cap wafer faces a corresponding front connection pad of the silicon integrated circuit substrate wafer;
then, performing a back grind to thin the silicon integrated circuit substrate wafer of the bonded wafer sandwich;
forming through silicon vias in the thinned silicon integrated circuit substrate wafer, wherein at least some of the through silicon vias are electrically connected to said at least one photosensitive region in each of the plurality of integrated circuit areas;
then, performing a back grind to thin the silicon cap wafer and expose the openings of the first and second trenches;
installing a light emitter integrated circuit die in the opening for each second trench, the light emitter integrated circuit die mounted to the thinned silicon integrated circuit substrate wafer and electrically connected to said at least one front connection pad;
filling the openings of the first and second trenches with a transparent material; and
cutting through the bonded wafer sandwich between adjacent integrated circuit areas in a singulation operation to produce a plurality of individual wafer level micro-sensor modules.
2 . The method of claim 1 , wherein providing the opaque light barrier comprises lining sidewalls and a bottom of each first trench and each second trench with an opaque material layer.
3 . The method of claim 1 , wherein providing the opaque light barrier comprises forming a trench in an upper surface of the silicon cap wafer between the first and second trenches, and filling the trench with an opaque material to form an opaque material block between the first and second trenches.
4 . The method of claim 1 , wherein providing the opaque light barrier comprises forming an annular trench in an upper surface of the silicon cap wafer around each of the first and second trenches, and filling each annular trench with an opaque material to form an opaque material ring around each of the first and second trenches.
5 . A method, comprising:
at each integrated circuit area of a plurality of integrated circuit areas for a silicon integrated circuit substrate wafer, forming at least one photosensitive region and at least one front connection pad;
covering each photosensitive region with a protective layer before wafer-to-wafer bonding;
forming a plurality of first trenches and a plurality of second trenches in a silicon cap wafer;
providing an opaque light barrier at the silicon cap wafer to block light transmission through the silicon cap wafer between the first and second trenches;
wafer-to-wafer bonding of the silicon cap wafer to the silicon integrated circuit substrate wafer to form a bonded wafer sandwich, where an opening of each first trench in the silicon cap wafer faces a corresponding photosensitive region of the silicon integrated circuit substrate wafer and wherein an opening of each second trench in the silicon cap wafer faces a corresponding front connection pad of the silicon integrated circuit substrate wafer;
then, performing a back grind to thin the silicon integrated circuit substrate wafer of the bonded wafer sandwich;
then, performing a back grind to thin the silicon integrated circuit substrate wafer of the bonded wafer sandwich;
forming through silicon vias in the thinned silicon integrated circuit substrate wafer, wherein at least some of the through silicon vias are electrically connected to said at least one photosensitive region in each of the plurality of integrated circuit areas;
then, performing a back grind to thin the silicon cap wafer and expose the openings of the first and second trenches;
removing the protective layer after performing the back grind to thin the silicon cap wafer;
installing a light emitter integrated circuit die in the opening for each second trench, the light emitter integrated circuit die mounted to the thinned silicon integrated circuit substrate wafer and electrically connected to said at least one front connection pad;
filling the openings of the first and second trenches with a transparent material; and
cutting through the bonded wafer sandwich between adjacent integrated circuit areas in a singulation operation to produce a plurality of individual wafer level micro-sensor modules.
6 . The method of claim 5 , wherein providing the opaque light barrier comprises lining sidewalls and a bottom of each first trench and each second trench with an opaque material layer.
7 . The method of claim 5 , wherein providing the opaque light barrier comprises forming a trench in an upper surface of the silicon cap wafer between the first and second trenches, and filling the trench with an opaque material to form an opaque material block between the first and second trenches.
8 . The method of claim 5 , wherein providing the opaque light barrier comprises forming an annular trench in an upper surface of the silicon cap wafer around each of the first and second trenches, and filling each annular trench with an opaque material to form an opaque material ring around each of the first and second trenches.
9 . A method, comprising:
at each integrated circuit area of a plurality of integrated circuit areas for a silicon integrated circuit substrate wafer, forming at least one photosensitive region and at least one front connection pad;
forming a plurality of first trenches and a plurality of second trenches in a silicon cap wafer;
providing an opaque light barrier at the silicon cap wafer to block light transmission through the silicon cap wafer between the first and second trenches;
wafer-to-wafer bonding of the silicon cap wafer to the silicon integrated circuit substrate wafer to form a bonded wafer sandwich, where an opening of each first trench in the silicon cap wafer faces a corresponding photosensitive region of the silicon integrated circuit substrate wafer and wherein an opening of each second trench in the silicon cap wafer faces a corresponding front connection pad of the silicon integrated circuit substrate wafer;
then, performing a back grind to thin the silicon integrated circuit substrate wafer of the bonded wafer sandwich;
forming through silicon vias in the thinned silicon integrated circuit substrate wafer, wherein at least some of the through silicon vias are electrically connected to said at least one photosensitive region in each of the plurality of integrated circuit areas;
then, performing a back grind to thin the silicon cap wafer and expose the openings of the first and second trenches;
installing a light emitter integrated circuit die in the opening for each second trench, the light emitter integrated circuit die mounted to the thinned silicon integrated circuit substrate wafer and electrically connected to said at least one front connection pad;
filling the openings of the first and second trenches with a transparent material;
after filling the openings of the first and second trenches with the transparent material, covering an upper surface of the thinned silicon cap wafer with a patterned layer of opaque material that includes apertures over each of the transparent material filled openings of the first and second trenches; and
cutting through the bonded wafer sandwich between adjacent integrated circuit areas in a singulation operation to produce a plurality of individual wafer level micro-sensor modules.
10 . The method of claim 9 , wherein providing the opaque light barrier comprises lining sidewalls and a bottom of each first trench and each second trench with an opaque material layer.
11 . The method of claim 9 , wherein providing the opaque light barrier comprises forming a trench in an upper surface of the silicon cap wafer between the first and second trenches, and filling the trench with an opaque material to form an opaque material block between the first and second trenches.
12 . The method of claim 9 , wherein providing the opaque light barrier comprises forming an annular trench in an upper surface of the silicon cap wafer around each of the first and second trenches, and filling each annular trench with an opaque material to form an opaque material ring around each of the first and second trenches.