Storage device for reducing reliability degradation of OS data through stage change before SMT process and method for operating the same
A method of operating a storage device for programming data into a flash memory before a surface mount technology (SMT) process is provided. The method includes: comparing program states of first memory cells connected to a first word line with program states of second memory cells connected to a second word line; changing the program states of the second memory cells according to a result of the comparing; and multi-bit programming the data and changed state information into the second memory cells.
1 . A method of operating a storage device for programming data into a flash memory before exposing to a high-temperature environment process, the method comprising:
comparing program states of first memory cells connected to a first word line with program states to be programmed to second memory cells connected to a second word line;
changing the program states to be programmed to the second memory cells according to a result of the comparing; and
multi-bit programming the changed program states and/or changed state information into the second memory cells,
wherein the comparing comprises comparing a difference value with a reference value, the difference value indicating a difference between the program states of the first memory cells and the program states to be programmed to the second memory cells, and the reference value being a natural number.
2 . The method of claim 1 , wherein the second word line is adjacent to the first word line.
3 . The method of claim 1 , wherein the reference value varies according to a position of the second word line.
4 . The method of claim 1 , further comprising identifying the reference value according to a spacing between the first word line and the second word line.
5 . The method of claim 1 , wherein the changing the program states comprises changing state indexes of the second memory cells.
6 . The method of claim 1 , wherein the changed program states are stored in a main field of the second memory cells, and the changed state information is stored in a spare field.
7 . The method of claim 1 , wherein the multi-bit programming is a triple-level cell (TLC) program operation that stores 3-bits in one memory cell.
8 . The method of claim 1 , further comprising performing a data migration operation to restore the program states of the second memory cells after the high-temperature environment process.
9 . The method of claim 1 , wherein memory cells of the flash memory are stacked in a vertical direction from a substrate.
10 . A method of operating a storage device for programming data into a flash memory before exposing to a high-temperature environment process, comprising:
programming first memory cells connected to a first word line;
reading first program states of the first memory cells;
checking second program states to be programmed to second memory cells connected to a second word line;
comparing the first program states with the second program states;
changing the second program states according to a result of the comparing; and
multi-bit programming the changed second program states and/or changed state information into the second memory cells,
wherein the comparing comprises comparing a difference value with a reference value, the difference value indicating a difference between the first program states of the first memory cells and the second program states to be programmed to the second memory cells, and the reference value being a natural number.
11 . The method of claim 10 , wherein the second word line is adjacent to the first word line.
12 . The method of claim 10 , further comprising identifying the reference value according to a position of the second word line.
13 . The method of claim 10 , further comprising identifying the reference value according to a spacing between the first word line and the second word line.
14 . A storage device comprising:
a flash memory comprising first memory cells connected to a first word line and second memory cells connected to a second word line; and
a memory controller configured to:
compare program states of the first memory cells with program states to be programmed to the second memory cells, change the program states to be programmed to the second memory cells according to a comparison result, and multi-bit program the changed program states and/or changed state information into the second memory cells; and
control a state index encoder to perform bit-encoding according to a result of a comparing a difference value with a reference value, the difference value indicating a difference between the program states of the first memory cells and the program states to be programmed to the second memory cells, and the reference value being a natural number.
15 . The storage device of claim 14 , wherein the memory controller is further configured to control:
the state index encoder to change the program states of the second memory cells before exposing to a high-temperature environment process; and
a state index decoder to restore the program states of the second memory cells after the high-temperature environment process.
16 . The storage device of claim 15 , wherein the memory controller is further configured to control the state index encoder to perform bit-encoding by changing state indexes of the second memory cells.
17 . The storage device of claim 14 , wherein the second word line is positioned between the first word line and a common source line.