Semiconductor cell architecture including backside power rails
Provided is a semiconductor cell architecture which includes a plurality of cells, a plurality of backside power rails, and a plurality of metal lines, wherein the backside power rails are extended in a cell-length direction, and at least one backside power rail vertically overlaps an inside area of at least one cell without vertically overlapping a lower boundary or an upper boundary of the at least one cell in a plan view.
1 . A semiconductor cell architecture comprising a plurality of cells, a plurality of backside power rails, and a plurality of metal lines,
wherein the backside power rails are extended in a cell-length direction,
wherein at least one backside power rail vertically overlaps an inside area of at least one cell without vertically overlapping a lower boundary or an upper boundary of the at least one cell in a plan view; and
wherein the at least one backside power rail vertically overlaps an upper boundary or a lower boundary of another at least one cell in the plan view.
2 . The semiconductor cell architecture of claim 1 , wherein the other at least one cell is adjacent to the at least one cell in the cell-length direction.
3 . The semiconductor cell architecture of claim 1 , wherein each of an upper boundary and a lower boundary of each cell vertically overlaps a respective backside power rail among the backside power rails in the plan view.
4 . The semiconductor cell architecture of claim 3 , wherein the cells have an equal cell height.
5 . The semiconductor cell architecture of claim 4 , wherein at least two adjacent cells in the cell-length direction do not share a side boundary at a full cell length.
6 . The semiconductor cell architecture of claim 1 , wherein a backside power rail positioned between two power rails in a cell-height direction provide a voltage different from voltages provided by the two power rails.
7 . The semiconductor cell architecture of claim 1 , wherein at least one of the backside power rails is configured to connect a corresponding cell to another circuit element which is not a voltage source.
8 . The semiconductor cell architecture of claim 1 , wherein the backside power rails are extended in the cell-length direction,
wherein the plurality of metal lines comprise a plurality of 1st metal lines extended in the-cell-length direction in a 1 st metal layer and a plurality of 2 nd metal lines extended in a cell-height direction in a 2 nd metal layer, and
wherein the 1 st metal lines are placed in at least one row defined by two adjacent backside power rails in the plan view.
9 . The semiconductor cell architecture of claim 8 , wherein a pitch of the backside power rails is greater than a pitch of the 1st metal lines.
10 . A semiconductor cell architecture comprising a plurality of cells, a plurality of backside power rails, and a plurality of metal lines,
wherein the cells have an equal cell height,
wherein the backside power rails are extended in a cell-length direction, and
wherein at least two adjacent cells in the cell-length direction do not share a side boundary at a full cell length.
11 . The semiconductor cell architecture of claim 10 , wherein at least one backside power rail traverses an inside of at least one cell in a plan view.
12 . The semiconductor cell architecture of claim 11 , wherein the at least one backside power rail vertically overlaps an upper boundary or a lower boundary of another at least one cell in the plan view.
13 . The semiconductor cell architecture of claim 12 , wherein each of an upper boundary and a lower boundary of each cell vertically overlaps a respective backside power rail among the backside power rails in the plan view.
14 . The semiconductor cell architecture of claim 13 , wherein the metal lines comprise 1st metal lines extended in a cell-length direction and 2 nd metal lines extended in a cell-height direction, and
wherein the 1 st metal lines do not vertically overlap the backside power rails in the plan view.
15 . A semiconductor cell architecture comprising a plurality of cells, a plurality of backside metal lines, and a plurality of metal lines,
wherein the backside metal lines are extended in a cell-length direction,
wherein the metal lines comprise a plurality of 1 st metal lines extended in the-cell length direction in a 1 st metal layer and a plurality of 2 nd metal lines extended in a cell-height direction in a 2 nd metal layer,
wherein the 1 st metal lines are placed in at least one row defined by two adjacent backside metal lines in a plan view; and
wherein a pitch of the backside metal lines is greater than a pitch of the 1 st metal lines.
16 . The semiconductor cell architecture of claim 15 , wherein at least two backside metal lines are backside power rails.
17 . The semiconductor cell architecture of claim 15 , wherein at least one backside metal line vertically overlaps an inside area of at least one cell without vertically overlapping a lower boundary or an upper boundary of the at least one cell.
18 . The semiconductor cell architecture of claim 17 , wherein each of an upper boundary and a lower boundary of each cell vertically overlaps a respective backside power rail among the backside power rails in the plan view.