Cell architecture
Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.
1. A device, comprising:
logic circuitry having transistors with gate lines; and
a backside power network having buried supply rails with at least one buried supply rail having a continuity break,
wherein the transistors are arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.
2. The device of claim 1 , wherein the transistors include:
a first column of transistors that are arranged in multiple rows, and
a second column of transistors that are arranged in multiple rows adjacent to the first column of transistors.
3. The device of claim 2 , wherein:
the first column of transistors includes a first number of transistors and a second number of transistors, and
the second column of transistors includes a third number of transistors that is greater than the first number of transistors.
4. The device of claim 3 , wherein:
the first number of transistors refers to multiple N-type transistors,
the second number of transistors refers to multiple P-type transistors, and
the third number of transistors refers to multiple N-type transistors that is greater than the first number of N-type transistors.
5. The device of claim 1 , wherein the gate lines refer to poly-silicon gate lines.
6. The device of claim 1 , further comprising:
frontside signal lines coupled to the transistors for signal routing; and
buried transition vias that couple the transistors to the buried supply rails.
7. The device of claim 6 , wherein:
the frontside signal lines are formed with frontside metal, and
the buried supply rails are formed with backside buried metal.
8. The device of claim 7 , wherein:
the backside buried metal is disposed underneath the frontside metal, and
the buried transition vias are disposed between the frontside metal and the backside buried metal.
9. The device of claim 6 , wherein:
the buried supply rails provide a backside power network to the transistors in the cell architecture, and
the buried transition vias are used to transition the backside power network to the transistors in the logic circuitry.
10. The device of claim 1 , wherein the backside power network is configured to provide a core voltage (VDD) and ground (VSS) to the transistors in the logic circuitry.
11. A cell architecture, comprising:
multiple regions including a first region with an N-well and a second region with an N-well break; and
transistors including a first column of transistors in the first region with the N-well and a second column of transistors in the second region with the N-well break.
12. The cell architecture of claim 11 , wherein:
the first column of transistors include a first number of N-type transistors and a second number of P-type transistors, and
the second column of transistors include a third number of N-type transistors that is greater than the first number of N-type transistors.
13. The cell architecture of claim 11 , further comprising:
a backside power network having buried supply rails with at least one buried supply rail having a continuity break in the second region with the N-well break,
wherein the second column of transistors are disposed in the second region with the N-well break and the continuity break.
14. The cell architecture of claim 13 , wherein:
the first column of transistors have first gate lines, and
the second column of transistors have second gate lines that pass through the N-well break and the continuity break in the at least one buried supply rail.
15. The cell architecture of claim 14 , wherein:
the first gate lines and the second gate lines refer to poly-silicon gate lines, and
the second gate lines are disposed in a manner so as to pass through an open spatial interval formed with the N-well break.
16. A method, comprising:
providing logic circuitry with transistors and gate lines; and
providing a backside power network with buried supply rails with at least one buried supply rail having a continuity break,
arranging the transistors in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.
17. The method of claim 16 , wherein the transistors include:
a first column of transistors that are arranged in multiple rows, and the first column of transistors has a first number of transistors and a second number of transistors, and
a second column of transistors that are arranged in multiple rows adjacent to the first column of transistors, and the second column of transistors has a third number of transistors that is greater than the first number of transistors.
18. The method of claim 17 , wherein:
the first number of transistors refers to multiple N-type transistors,
the second number of transistors refers to multiple P-type transistors, and
the third number of transistors refers to multiple N-type transistors that is greater than the first number of N-type transistors.
19. The method of claim 16 , further comprising:
providing frontside signal lines coupled to the transistors for signal routing; and
providing buried transition vias that couple the transistors to the buried supply rails.
20. The method of claim 16 , wherein the gate lines refer to poly-silicon gate lines.