Semiconductor element memory device
View Patent ↗A semiconductor-element-including semiconductor memory device includes a block in which a plurality of memory cells CL 00 to CL 13 are arranged in a matrix, in which a data retention operation is performed in which voltages applied to plate lines PL 0 and PL 1 , word lines WL 0 and WL 1 , a source line SL, and bit lines BL 0 to BL 3 are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the plate lines PL 0 and PL 1 , the word lines WL 0 and WL 1 , the source line SL, and the bit lines BL 0 to BL 3 are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the plate lines PL 0 and PL 1 and capacitive coupling with the word lines WL 0 and WL 1 . For the memory cells in the block, one or both of a memory re-write operation for the memory cells CL 00 , CL 02 , CL 03 , CL 11 , and CL 13 that are in a state of the data retention operation and a memory re-erase operation for the memory cells CL 01 , CL 10 , and CL 12 in a state of the data erase operation are performed for all of the memory cells in the block simultaneously.
1. A semiconductor element memory device comprising a block constituted by a plurality of memory cells arranged in a matrix on a substrate, each of the memory cells included in the block comprising:
a semiconductor body formed to stand on the substrate in a vertical direction relative to the substrate or extend in a horizontal direction relative to the substrate;
a first impurity region and a second impurity region formed to be disposed, respectively, at ends of the semiconductor body;
a gate insulator layer formed in contact with a side surface of the semiconductor body between the first impurity region and the second impurity region;
a first gate conductor layer formed to at least partially cover the gate insulator layer; and
a second gate conductor layer formed adjacent to the first gate conductor layer in contact with a side surface of the gate insulator layer, wherein in each of the memory cells,
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to retain, inside the semiconductor body, a group of positive holes, which are generated by an impact ionization phenomenon or a gate-induced drain leakage current,
a memory write operation is performed in which a voltage of the semiconductor body is made equal to a first data retention voltage that is higher than the voltage of one of the first impurity region or the second impurity region or the voltages of both of the first impurity region and the second impurity region by a built-in voltage,
a memory erase operation is performed in which the voltage of the semiconductor body is controlled so as to be higher than the first data retention voltage with first capacitive coupling between the first gate conductor layer and the semiconductor body and second capacitive coupling between the second gate conductor layer and the semiconductor body, and a group of remaining positive holes among the group of positive holes are discharged from inside the semiconductor body through one or both of the first impurity region and the second impurity region until the voltage of the semiconductor body becomes equal to a voltage higher than the voltage of one of the first impurity region or the second impurity region or the voltages of both of the first impurity region and the second impurity region by the built-in voltage, and
further wherein the voltage of the semiconductor body is made equal to a second data retention voltage lower than the first data retention voltage with the first capacitive coupling and the second capacitive coupling,
the voltage of the semiconductor body in each of the plurality of memory cells in the block is equal to the first data retention voltage or the second data retention voltage at a first time,
at a second time after a lapse of time since the first time, a memory re-write operation is performed for the semiconductor body, in the block, that is at a voltage equal to the first data retention voltage at the first time to return the voltage of the semiconductor body to a voltage close to the first data retention voltage, and
at a third time after a lapse of time since the first time, a memory re-erase operation is performed for the semiconductor body, in the block, that is at a voltage equal to the second data retention voltage at the first time to return the voltage of the semiconductor body to a voltage close to the second data retention voltage.
2. The semiconductor element memory device according to claim 1 , wherein the voltage of the first gate conductor layer is increased from a first voltage to a second voltage higher than the first voltage, and the voltage of the second gate conductor layer is increased from a third voltage to a fourth voltage higher than the third voltage,
the memory re-erase operation is performed over a first period, a second period, and a third period,
in the first period, the voltage of the semiconductor body is controlled so as to be higher than the voltage at the first time with the first capacitive coupling and the second capacitive coupling,
in the second period, the group of remaining positive holes among the group of positive holes are discharged from inside the semiconductor body through one or both of the first impurity region and the second impurity region until the voltage of the semiconductor body becomes equal to a voltage higher than the voltage of one of the first impurity region or the second impurity region or the voltages of both of the first impurity region and the second impurity region by the built-in voltage, and
in the third period, the voltage of the semiconductor body is made equal to a voltage close to the second data retention voltage lower than the first data retention voltage with the first capacitive coupling and the second capacitive coupling.
3. The semiconductor element memory device according to claim 2 , wherein the voltage of the first gate conductor layer is increased from the first voltage to the second voltage in increments of a first step voltage in at least two steps, the voltage of the second gate conductor layer is increased from the third voltage to the fourth voltage in increments of a second step voltage in at least two steps, and the memory re-erase operation is performed.
4. The semiconductor element memory device according to claim 1 , wherein in the memory re-write operation, an inversion layer is formed in the semiconductor body, in the same block, that is at a voltage equal to the first data retention voltage at the first time, and the semiconductor body is kept at a voltage close to the first data retention voltage.
5. The semiconductor element memory device according to claim 1 , wherein in the memory re-erase operation, in the semiconductor body, in the same block, that is at a voltage equal to the second data retention voltage at the first time, a current does not flow between the first impurity region and the second impurity region, and the semiconductor body is kept at a voltage close to the second data retention voltage.
6. The semiconductor element memory device according to claim 1 , wherein a first gate capacitance between the first gate conductor layer and the semiconductor body is larger than a second gate capacitance between the second gate conductor layer and the semiconductor body.
7. A semiconductor element memory device comprising a group of blocks that are a plurality of blocks each of which is the block of the semiconductor element memory device according to claim 1 , wherein
the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line,
the source line is connected to the semiconductor bodies in each of the blocks, and
voltages are applied to the source line, the bit line, the first driving control line, and the word line to perform one of the memory re-write operation or the memory re-erase operation for all of the semiconductor bodies in a block selected from among the group of blocks or simultaneously perform both of the memory re-write operation and the memory re-erase operation for all of the semiconductor bodies in respective blocks selected from among the group of blocks.
8. The semiconductor element memory device according to claim 1 , wherein one or both of the first gate conductor layer and the second gate conductor layer is divided into two or more isolated gate conductor layers in plan view or in the vertical direction, and the isolated gate conductor layers are operated synchronously or asynchronously.
9. The semiconductor element memory device according to claim 8 , wherein in the vertical direction, the isolated gate conductor layers obtained from one of the first gate conductor layer or the second gate conductor layer are disposed on respective sides of the other of the first gate conductor layer or the second gate conductor layer.