Semiconductor-element-including memory device
View Patent ↗A memory device includes pages each constituted by memory cells on a substrate. Voltages applied to first and second gate conductor layers and impurity layers in each memory cell are controlled to retain positive holes inside a channel semiconductor layer. In a page write operation, the voltage of the channel semiconductor layer is set to a first data retention voltage. In a page erase operation, the applied voltages are controlled to discharge the positive holes, and the voltage of the channel semiconductor layer is set to a second data retention voltage. At a second time after a first time, a memory re-erase operation is performed for the channel semiconductor layers at the second data retention voltage at the first time. At a third time after the second time, a memory re-write operation is performed for the channel semiconductor layers at the first data retention voltage at the first time.
1. A semiconductor-element-including memory device, the memory device comprising a plurality of pages arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction on a substrate,
each of the memory cells included in each of the pages comprising:
a semiconductor base material that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction;
a first impurity layer and a second impurity layer that are disposed at respective ends of the semiconductor base material;
a first gate insulating layer that partially or entirely surrounds a side surface of the semiconductor base material between the first impurity layer and the second impurity layer and that is in contact with or in close vicinity to the first impurity layer;
a second gate insulating layer that surrounds the side surface of the semiconductor base material, that is connected to the first gate insulating layer, and that is in contact with or in close vicinity to the second impurity layer;
a first gate conductor layer that partially or entirely covers the first gate insulating layer;
a second gate conductor layer that partially or entirely covers the second gate insulating layer; and
a channel semiconductor layer that is the semiconductor base material and that is covered by the first gate insulating layer and the second gate insulating layer, wherein
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to retain a group of positive holes, inside the channel semiconductor layer, generated by an impact ionization phenomenon,
in a page write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage that is higher than the voltage of either the first impurity layer or the second impurity layer or that is higher than the voltages of both the first impurity layer and the second impurity layer,
in a page erase operation, the voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer are controlled to discharge the group of positive holes through either the first impurity layer or the second impurity layer or both the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is made equal to a second data retention voltage that is lower than the first data retention voltage,
the voltage of the channel semiconductor layer that is the semiconductor base material in each of the plurality of memory cells in each of the pages is equal to the first data retention voltage or the second data retention voltage at a first time,
at a second time after a lapse of time since the first time, a memory re-erase operation is performed for the semiconductor base material of the channel semiconductor layer, in the pages, that is at a voltage equal to the second data retention voltage at the first time to perform a first refresh operation of returning the voltage of the channel semiconductor layer to a voltage close to the second data retention voltage, and
at a third time after a lapse of time since the second time, a memory re-write operation is performed for the semiconductor base material of the channel semiconductor layer, in the pages, that is at a voltage equal to the first data retention voltage at the first time to perform a second refresh operation of returning the voltage of the channel semiconductor layer to a voltage close to the first data retention voltage.
2. The semiconductor-element-including memory device according to claim 1 , wherein a first gate capacitance between the first gate conductor layer and the channel semiconductor layer is larger than a second gate capacitance between the second gate conductor layer and the channel semiconductor layer.
3. The semiconductor-element-including memory device according to claim 1 , wherein the first gate conductor layer is isolated into at least two conductor layers around the first gate insulating layer when viewed in an axial direction of the semiconductor base material.
4. The semiconductor-element-including memory device according to claim 1 , wherein the impact ionization phenomenon occurs inside the channel semiconductor layer between the first gate conductor layer and the second gate conductor layer to generate the group of positive holes inside the channel semiconductor layer.
5. The semiconductor-element-including memory device according to claim 1 , wherein
the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line, and the word line and the first driving control line are connected to a row decoder circuit,
the source line is connected to the semiconductor base materials in each block in the group of blocks, and
voltages applied to the source line, the bit line, the first driving control line, and the word line are controlled to perform either the memory re-write operation or the memory re-erase operation or simultaneously perform both the memory re-write operation and the memory re-erase operation for all the semiconductor base materials in a block selected from among the group of blocks.
6. The semiconductor-element-including memory device according to claim 5 , wherein in the first refresh operation and in the second refresh operation, an all-word-line selection signal and an all-plate-line selection signal are input to the row decoder circuit to select all the word lines and all the first driving control lines in the block.
7. The semiconductor-element-including memory device according to claim 5 , wherein the first driving control line is arranged as a common driving control line for the memory cells adjacent to each other.
8. The semiconductor-element-including memory device according to claim 5 , wherein the source line is isolated into source lines each of which is for the memory cells that are arranged in the column direction and which are disposed parallel to the word lines and the first driving control line.
9. The semiconductor-element-including memory device according to claim 5 , wherein in a page sum-of-products read operation in which at least two word lines are selected in a multiple selection, the first refresh operation and the second refresh operation are performed in advance at least once for the word lines selected in a multiple selection in the page sum-of-products read operation.