Circuit board and manufacturing method thereof
A circuit board including: an insulation layer having a first surface and a second surface facing each other; a first pad layer including a first connection pad and a first conductive layer stacked on the first connection pad, a portion of the first pad layer buried in the insulation layer, and another portion of the first pad layer protruding from a first surface of the insulation layer; and a second conductive layer disposed on the first conductive layer.
1 . A circuit board comprising: an insulation layer having a first surface and a second surface facing each other; a first pad layer including a first connection pad and a first conductive layer stacked on the first connection pad, a portion of the first pad layer being buried in the insulation layer, and another portion of the first pad layer protruding from the first surface of the insulation layer; a second conductive layer disposed on the first pad layer and the first conductive layer; and a solder resist layer disposed on the insulation layer such that the solder resist layer is spaced apart from the first conductive layer, wherein the first pad layer is disposed in a bond finger region, wherein, in a thickness direction of the insulating layer, a central portion of a lower surface of the first connection pad directly contacts the insulation layer, wherein the insulation layer includes a plurality of insulation layers, and the plurality of insulation layers include a plurality of circuit layers thereon, wherein the solder resist layer is disposed adjacent to the bond finger region and on at least one circuit layer among the plurality of circuit layers, wherein an upper surface of the insulation layer disposed in the bond finger region is lower than an upper surface of the insulation layer adjacent to the bond finger region, and wherein the second conductive layer covers a lateral surface of the first conductive layer protruding from the first surface.
2 . The circuit board of claim 1 , wherein
the first connection pad is buried in the insulation layer, and an upper surface of the first connection pad is recessed into the insulation layer.
3 . The circuit board of claim 2 , wherein
the first conductive layer overlaps the upper surface of the first connection pad in the thickness direction of the insulation layer, and a portion of the first conductive layer is buried in the insulation layer and another portion of the first conductive layer protrudes from the first surface.
4 . The circuit board of claim 3 , wherein
the second conductive layer is disposed on an upper surface of the first conductive layer protruding from the first surface.
5 . The circuit board of claim 1 , wherein
the first connection pad includes a copper (Cu) layer.
6 . The circuit board of claim 1 , wherein
the first conductive layer includes a nickel (Ni) plating layer.
7 . The circuit board of claim 1 , wherein
the second conductive layer includes a gold (Au) plating layer.
8 . The circuit board of claim 1 , wherein
a width of the first conductive layer is substantially equal to a width of the first connection pad.
9 . A method of manufacturing the circuit board of claim 1 , comprising:
providing an embedded pattern substrate including the insulation layer, and the first connection pad buried in the insulation layer to be recessed into the insulation layer;
forming the first pad layer by stacking the first conductive layer on the first connection pad to overlap the first connection pad;
etching the insulation layer such that the first surface of the insulation layer is disposed between an upper surface and a lower surface of the first pad layer; and
forming a second conductive layer on the first conductive layer.
10 . The method of claim 9 , further comprising, before the providing of the embedded pattern substrate,
forming the embedded pattern substrate including
burying the first connection pad in the insulation layer, and
etching an upper surface of the first connection pad to be recessed into the insulation layer.
11 . The method of claim 9 , wherein
the etching of the insulation layer includes etching using a plasma treatment process.
12 . The method of claim 9 , wherein
the etching of the insulation layer includes
forming an upper surface of the first connection pad to be recessed into the insulation layer; and
forming an upper surface of the first conductive layer to be higher than the first surface of the insulation layer.
13 . The method of claim 9 , wherein
the etching of the insulation layer is performed such that the first conductive layer protrudes from the insulation layer, and then the forming of the second conductive layer includes plating the second conductive layer on the first conductive layer to form the second conductive layer.
14 . The method of claim 9 , wherein
the forming of the second conductive layer includes plating the second conductive layer on the first conductive layer before the etching of the insulation layer.