Semiconductor element memory device
View Patent ↗A memory device uses semiconductor elements. By controlling voltages applied to plate lines, word lines, source lines, and bit lines, the memory device performs a data write operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a data erase operation of removing positive hole groups from inside the semiconductor base material. The memory device includes a block made up of memory cells, which are arrayed in a matrix. Storage data of memory cells connected with a first word line, i.e., a selected one of the word lines, in the block is read to the bit lines by applying a first voltage to the first word line, and a second voltage to a second word line adjacent to the first word line.
1. A semiconductor memory device comprising a block in which a plurality of semiconductor memory cells is arrayed in a matrix, each of the semiconductor memory cells including:
semiconductor base material erected on a substrate in a vertical direction of the substrate or extended on the substrate in a horizontal direction,
a first impurity region and a second impurity region provided on opposite ends of the semiconductor base material;
a gate insulating layer placed in contact with a lateral surface of the semiconductor base material between the first impurity region and the second impurity region;
a first gate conductor layer covering part or all of the gate insulating layer; and
a second gate conductor layer located adjacent to the first gate conductor layer and placed in contact with a lateral surface of the gate insulating layer,
wherein positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current are held in the semiconductor base material by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region,
a memory write operation is performed by setting a voltage of the semiconductor base material to a first data retention voltage,
a memory erase operation is performed by controlling voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer and thereby extracting a residual positive hole group out of the positive hole groups from one or both of the first impurity region and the second impurity region,
the voltage of the semiconductor base material is set to a second data retention voltage lower than the first data retention voltage, and
in the block,
in each of the semiconductor memory cells, the first impurity region is connected with a source line, the second impurity region is connected with a bit line, and one of the first gate conductor layer and the second gate conductor layer is connected with word lines and another is connected with a first drive control line, and
with a selected one of the word lines being designated as a first word line and a word line adjacent to the first word line being designated as a second word line, using a voltage applied to the source line, the bit line, and the first drive control line, a first voltage applied to the first word line, and a second voltage applied to the second word line, a memory read operation is performed to read storage data of a plurality of the semiconductor memory cells selected by the first word line, to the bit line.
2. The semiconductor memory device according to claim 1 , wherein with a word line adjacent to the first word line and located on an opposite side of the second word line being designated as a third word line, using a voltage applied to the source line, the bit line, and the first drive control line, the first voltage applied to the first word line, and a second voltage applied to one or both of the second word line and the third word line, a memory read operation is performed to read storage data of the plurality of semiconductor memory cells selected by the first word line, to the bit line.
3. The semiconductor memory device according to claim 1 , wherein the storage data of the semiconductor base material is read to the bit line and a sense amplifier circuit determines whether the storage data is write data or erase data.
4. The semiconductor memory device according to claim 1 , wherein the first voltage is a positive voltage and the second voltage is a negative voltage.
5. The semiconductor memory device according to claim 2 , wherein one or both of the second word line and the third word line turn(s) to the second voltage at a first time point, the first word line turns to the first voltage at a second time point later than the first time point, and a memory read operation is performed to read storage data of the plurality of semiconductor memory cells selected by the first word line, to the bit line.
6. The semiconductor memory device according to claim 5 , wherein one or both of the second word line and the third word line turn(s) to the negative voltage at the first time point, the first word line turns to the positive voltage at the second time point, and a memory read operation is performed to read storage data of the plurality of semiconductor memory cells selected by the first word line, to the bit line.
7. The semiconductor memory device according to claim 1 , wherein the first drive control line is common to all the semiconductor memory cells making up the block.
8. The semiconductor memory device according to claim 1 , wherein first gate capacitance between the first gate conductor layer and the semiconductor base material is higher than second gate capacitance between the second gate conductor layer and the semiconductor base material.
9. The semiconductor memory device according to claim 1 , wherein one or both of the first gate conductor layer and the second gate conductor layer are divided into two or more separate gate conductor layers in planar view or in a vertical direction and the separate gate conductor layers are operated synchronously or asynchronously.
10. The semiconductor memory device according to claim 9 , wherein in the vertical direction, either the separate gate conductor layers of the first gate conductor layer are placed on opposite sides of the second gate conductor layer, or the separate gate conductor layers of the second gate conductor layer are placed on opposite sides of the first gate conductor layer.