Semiconductor package
A semiconductor package includes a first semiconductor chip, a lower redistribution structure electrically connected to the first semiconductor chip, an upper redistribution structure on the first semiconductor chip, a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure, and a first wire connecting a lower surface of the first semiconductor chip with an upper surface of the lower redistribution structure to dissipate heat of the first semiconductor chip.
1 . A semiconductor package comprising:
a first semiconductor chip;
a lower redistribution structure electrically connected to the first semiconductor chip;
an upper redistribution structure on the first semiconductor chip;
a molding layer between the lower redistribution structure and the upper redistribution structure, the molding layer surrounding side surfaces of the first semiconductor chip and a lower surface of the first semiconductor chip;
a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure; and
at least one first wire connecting a lower surface of the first semiconductor chip to an upper surface of the lower redistribution structure, the at least one first wire extending, in the molding layer, between the lower surface of the first semiconductor chip and the upper surface of the lower redistribution structure.
2 . The semiconductor package of claim 1 , wherein the first semiconductor chip is electrically connected to the lower redistribution structure via a conductive bump, and
wherein the conductive bump is in the molding layer between the lower surface of the first semiconductor chip and the upper surface of the lower redistribution structure.
3 . The semiconductor package of claim 1 , wherein the at least one first wire comprises an inner first wire and an outer first wire arranged radially with respect to a center portion of the first semiconductor chip.
4 . The semiconductor package of claim 1 , wherein the at least one first wire connects the lower surface of the first semiconductor chip to a portion of the upper surface of the lower redistribution structure, the portion not overlapping with the first semiconductor chip.
5 . The semiconductor package of claim 1 , wherein the at least one first wire connects the lower surface of the first semiconductor chip to a portion of the upper surface of the lower redistribution structure, the portion overlapping with the first semiconductor chip.
6 . The semiconductor package of claim 1 , wherein the at least one first wire comprises a plurality of first wires, and adjacent ones of the plurality of first wires are spaced apart uniformly from each other.
7 . The semiconductor package of claim 1 , wherein the at least one first wire comprises a plurality of first wires that are provided in a first region and a second region, wherein a density of the plurality of first wires in the first region is greater than a density of the plurality of first wires in the second region.
8 . The semiconductor package of claim 1 , further comprising a second semiconductor chip on an upper surface of the upper redistribution structure and electrically connected to a redistribution layer of the semiconductor package.
9 . The semiconductor package of claim 1 , wherein the first semiconductor chip is electrically connected to the lower redistribution structure via a conductive pad.
10 . A semiconductor package comprising:
a first semiconductor chip;
a lower redistribution structure electrically connected to the first semiconductor chip;
an upper redistribution structure on the first semiconductor chip;
a molding layer between the lower redistribution structure and the upper redistribution structure, the molding layer surrounding side surfaces of the first semiconductor chip and a lower surface of the first semiconductor chip;
a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure;
at least one first wire connecting a lower surface of the first semiconductor chip to an upper surface of the lower redistribution structure, the at least one first wire extending, in the molding layer, between the lower surface of the first semiconductor chip and the upper surface of the lower redistribution structure; and
at least one second wire connecting the upper surface of the lower redistribution structure to a lower surface of the upper redistribution structure, the at least one second wire extending, in a portion of the molding layer that surrounds the side surfaces of the first semiconductor chip, between the upper surface of the lower redistribution structure and the lower surface of the upper redistribution structure.
11 . The semiconductor package of claim 10 , wherein at least a portion of the at least one second wire electrically connects the upper surface of the lower redistribution structure to the lower surface of the upper redistribution structure.
12 . The semiconductor package of claim 10 , wherein the at least one second wire comprises one or more from among gold (Au), silver (Ag), and copper (Cu).
13 . The semiconductor package of claim 10 , wherein a total number of the at least one first wire is equal to a total number of the at least one second wire.
14 . The semiconductor package of claim 10 , wherein the at least one first wire comprises an inner first wire and an outer first wire arranged radially with respect to a center portion of the first semiconductor chip.
15 . The semiconductor package of claim 10 , wherein the at least one second wire comprises an inner second wire and an outer second wire arranged radially with respect to a center portion of the first semiconductor chip.
16 . The semiconductor package of claim 10 , wherein the at least one first wire connects the lower surface of the first semiconductor chip to a portion of the upper surface of the lower redistribution structure, the portion not overlapping with the first semiconductor chip.
17 . The semiconductor package of claim 10 , wherein at least one from among the at least one first wire and the at least one second wire comprises a plurality of wires that are provided in a first region and a second region, wherein a density of the plurality of wires in the first region is greater than a density of the plurality of wires in the second region.
18 . The semiconductor package of claim 10 , wherein the at least one first wire comprise a pair of first wires that are connected to the lower surface of the first semiconductor chip.
19 . The semiconductor package of claim 10 , further comprising a second semiconductor chip on an upper surface of the upper redistribution structure and electrically connected to a redistribution layer of the semiconductor package.
20 . A semiconductor package comprising:
a first semiconductor chip;
a lower redistribution structure electrically connected to the first semiconductor chip;
an upper redistribution structure on the first semiconductor chip;
a molding layer between the lower redistribution structure and the upper redistribution structure, the molding layer surrounding side surfaces of the first semiconductor chip and a lower surface of the first semiconductor chip;
a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure;
a second semiconductor chip on an upper surface of the upper redistribution structure and electrically connected to a redistribution layer of the semiconductor package;
at least one first wire connecting a lower surface of the first semiconductor chip with an upper surface of the lower redistribution structure, the at least one first wire extending, in the molding layer, between the lower surface of the first semiconductor chip and the upper surface of the lower redistribution structure; and
at least one second wire connecting the upper surface of the lower redistribution structure to a lower surface of the upper redistribution structure, the at least one second wire extending, in a portion of the molding layer that surrounds the side surfaces of the first semiconductor chip, between the upper surface of the lower redistribution structure and the lower surface of the upper redistribution structure,
wherein at least a portion of the at least one second wire electrically connects the upper surface of the lower redistribution structure to the lower surface of the upper redistribution structure, and
wherein a total number of the at least one first wire is equal to a total number of the at least one second wire.