Memory apparatus using semiconductor devices
View Patent ↗A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and to input page data for the page write operation to a sense amplifier circuit during the page erase operation.
1. A memory apparatus using semiconductor devices, comprising a block including a plurality of memory cells arranged in a matrix on a substrate, the block including a page formed by memory cells arranged in a column among the plurality of memory cells,
wherein:
each memory cell included in the page has
a semiconductor base material provided on the substrate in a manner standing in an upright position along a vertical direction or extending in a horizontal direction with respect to the substrate,
a first impurity region and a second impurity region at opposite ends of the semiconductor base material,
a gate insulating layer in contact with a side face of the semiconductor base material between the first impurity region and the second impurity region,
a first gate conductor layer partially or entirely covering the gate insulating layer, and
a second gate conductor layer adjacent to the first gate conductor layer and in contact with a side face of the gate insulating layer,
in each of the individual memory cells,
each of voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region is controlled to allow holes generated through an impact ionization phenomenon or using a gate induced drain leakage current to be retained in the semiconductor base material,
during a page write operation, a voltage of the semiconductor base material is set to a first data holding voltage that is higher than one or both of a voltage of the first impurity region and a voltage of the second impurity region, and
during a page erase operation, each of voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer is controlled to allow the holes to be pulled out through one or both of the first impurity region and the second impurity region, and then, the voltage of the semiconductor base material is set to a second data holding voltage lower than the first data holding voltage,
the first impurity region in each of the memory cells connects to a source line, the second impurity region connects to a bit line, one of the first gate conductor layer and the second gate conductor layer connects to a word line, and another of the first gate conductor layer and the second gate conductor layer connects to a first drive control line,
the bit line connects to a sense amplifier circuit via a first switch circuit, and
during the page erase operation, page data for the page write operation is input to the sense amplifier circuit.
2. The memory apparatus using the semiconductor devices according to claim 1 , wherein during the page erase operation, the first switch circuit is turned off to non-conductive state, and the page data is input to the sense amplifier circuit.
3. The memory apparatus using the semiconductor devices according to claim 1 ,
wherein:
during the page erase operation, the first switch circuit is turned off to non-conductive state, and the page data is input to the sense amplifier circuit, and
when the page erase operation is complete, the first switch circuit is turned on to conductive state, and the page write operation is performed.
4. The memory apparatus using the semiconductor devices according to claim 1 , wherein during the page erase operation, the voltage of the semiconductor base material in each of the memory cells in the page is set to the second data holding voltage.
5. The memory apparatus using the semiconductor devices according to claim 1 , wherein during the page write operation, the voltage of the semiconductor base material in each of the memory cells in the page is set to the first data holding voltage.
6. The memory apparatus using the semiconductor devices according to claim 1 , wherein during the page erase operation, the first switch circuit is turned off to non-conductive state, and the page data stored in the sense amplifier circuit is read.
7. The memory apparatus using the semiconductor devices according to claim 6 , wherein the page data stored in the sense amplifier circuit is memory data read from a memory cell before the page erase operation is started.
8. The memory apparatus using the semiconductor devices according to claim 1 , wherein a first gate capacitance between the first gate conductor layer and the semiconductor base material is set larger than a second gate capacitance between the second gate conductor layer and the semiconductor base material.
9. The memory apparatus using the semiconductor devices according to claim 1 , wherein during the page erase operation, the holes are removed from the semiconductor base material through the second impurity region, and the first impurity region is set to a floating state.
10. The memory apparatus using the semiconductor devices according to claim 1 , wherein during the page erase operation, the holes are removed from the semiconductor base material through the second impurity region, and the first impurity region is set to a ground voltage.
11. The memory apparatus using the semiconductor devices according to claim 1 , wherein one or both of the first gate conductor layer and the second gate conductor layer is/are split into two or more split gate conductor layers as seen in plan view or in the vertical direction, and the split two or more gate conductor layers are operated synchronously or asynchronously.
12. The memory apparatus using the semiconductor devices according to claim 11 , wherein the split gate conductor layers of one of the first gate conductor layer and the second gate conductor layer are arranged on opposite sides of another of the first gate conductor layer or the second gate conductor layer in the vertical direction.