Semiconductor-element-including memory device
View Patent ↗A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit.
1. A semiconductor memory device comprising a plurality of memory cells arranged in a matrix having rows and columns, each row representing a page of memory and the plurality of memory cells forming a plurality of pages of memory arranged in columns, each of the plurality of memory cell comprising:
a columnar semiconductor base being extensive for a length and supported by a substrate;
a first impurity region and a second impurity region connected by the columnar semiconductor base so that the first and second impurity regions are located, respectively, at end portions of the length of the columnar semiconductor base, wherein the first and second impurity regions are doped with impurities to have an identical conductive type;
a first gate conductor layer and a second gate conductor layer formed separately from each other along the length of the columnar semiconductor body and arranged at least partially around the columnar semiconductor body, wherein at least one of the first gate conductor layer or the second gate conductor layers is divided into a plurality of subsets of gate conductor layers;
at least one gate insulator provided to insulate the first and second gate conductor layers from the semiconductor columnar body, wherein the first and second gate conductor layers, the first impurity region, and the second impurity region individually provide terminals of the semiconductor memory device, a set of data write biases is applied in a page write operation across the terminals to generate majority carriers, as memory data charges, inside the columnar semiconductor body by either an occurrence of an impact ionization phenomenon or by means a gate-induced drain leakage current, and a set of data erase biases is applied in a page erase operation across the terminals to draw the majority carriers out of the columnar semiconductor body,
the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line,
in a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and
in at least one of the page write operation, the page erase operation, or the page read operation, a bias applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference bias generating circuit combined with a temperature-compensating circuit.
2. The semiconductor memory device according to claim 1 , wherein the first gate conductor layer is divided into two subsets of first gate conductor layers that each function as a conductive electrode of a plate line and are applied with either an identical bias or different biases to operate synchronously or asynchronously with each other.
3. The semiconductor memory device according to claim 1 , wherein the second gate conductor layer is divided into two subsets of second gate conductor layers that each function as a conductive electrode of a word line and are applied with either an identical bias or different biases to operate synchronously or asynchronously with each other.
4. The semiconductor memory device according to claim 2 , wherein at least one of the two subsets of first gate conductor layers is operated to function as the first gate conductor layer.
5. The semiconductor memory device according to claim 3 , wherein at least one of the two subsets of second gate conductor layers is operated to function as the second gate conductor layer.
6. The semiconductor memory device according to claim 1 , wherein the first gate conductor layer is connected to a word line, and the second gate conductor layer is connected to a plate line.