Field effect transistor with shallow trench isolation features within source/drain regions
The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.
1. A structure comprising:
at least one gate structure on an underlying substrate material, the at least one gate structure comprising two gate structures;
source/drain regions on opposing sides of each of the two gate structures;
at least one shallow trench isolation structure perpendicular to and positioned between and contacting the source/drain regions between adjacent sides of the two gate structures; and
a polysilicon layer under the source/drain regions of each of the two gate structures, which includes a portion contacting the at least one shallow trench isolation structure,
wherein the at least one shallow trench isolation structure is between the two gate structures, and
wherein the at least one shallow trench isolation structure comprises multiple shallow trench isolation structures, the multiple isolation structures comprise a first isolation structure positioned between the two gate structures and second isolation structures on sides of the two gate structures opposing the first isolation structure, each of which are contacting the polysilicon layer, and
wherein the at least one shallow trench isolation structure extends deeper into the substrate material than the source/drain regions, and the portion of the polysilicon layer extends upward toward a surface of the underlying substrate material and in combination with remaining portions of polysilicon layer forms a T-shape.
2. The structure of claim 1 , further comprising silicided semiconductor material in the source/drain regions adjacent to the at least one shallow trench isolation structure.
3. The structure of claim 2 , further comprising an interconnect structure landing on both the at least one shallow trench isolation structure and the silicided semiconductor material in the source/drain regions.
4. The structure of claim 3 , wherein the at least one gate structure comprises silicided polysilicon material.
5. The structure of claim 3 , wherein the at least one gate structure comprises metal material.
6. The structure of claim 1 , wherein the polysilicon layer is below the at least one shallow trench isolation structure and the source/drain regions and the at least one shallow trench isolation structure is located between the two gate structures at opposing sides of the two gate structures, the polysilicon material contacting the shallow trench isolation structure located between the two gate structures and on the opposing sides of the two gate structures.
7. The structure of claim 1 , wherein the source/drain regions extend into a single well for each of the gate structures, above the polysilicon layer, and wherein the at least one shallow trench isolation structure extends below the single well and source/drain regions.
8. The structure of claim 1 , wherein the first isolation structure comprises a depth shallower than the second isolation structures, and the first isolation structure and the second isolation structures directly contact the polysilicon layer below the two gate structures.
9. The structure of claim 1 , wherein the at least one gate structure comprises sidewall spacers and the at least one shallow trench isolation structure is remotely position from the sidewall spacers.
10. A structure comprising:
an implanted layer within a semiconductor substrate;
a dopant well within the semiconductor substrate;
at least two gate structures above the dopant well;
source/drain regions in the dopant well between the at least two gate structures and at sides of the at least two gate structures;
a shallow trench isolation structure extending below the dopant well within the semiconductor substrate, deeper than the source/drain regions and contacting the implanted layer;
a second isolation structure extending below the dopant well and within the semiconductor substrate, deeper than the source/drain regions and the shallow trench isolation structure, the second isolation structure also contacting the implanted layer; and
an interconnect structure that lands over the source/drain regions and aligned over the shallow trench isolation structure,
wherein the interconnect structure comprises a contact to the source/drain regions and which is aligned over the shallow trench isolation structure between the two gate structures, and
wherein the shallow trench isolation structure is-between the well structure and the implanted layer under the source/drain regions and silicide regions on both sides of the contact, and directly contacting the source/drain regions.
11. The structure of claim 10 , wherein the shallow trench isolation structure contacts the implanted layer between the at least two gate structures.
12. The structure of claim 10 , wherein the implanted layer comprises a high resistivity layer of semiconductor substrate of >1000 ohm-cm.
13. The structure of claim 12 , wherein the high resistivity layer comprises a resistivity greater than a resistivity of the semiconductor substrate.
14. The structure of claim 10 , wherein the implanted layer comprises polysilicon.
15. The structure of claim 10 , wherein the implanted layer is an argon implanted layer.
16. A method comprising:
forming two gate structures on an underlying substrate material;
forming source/drain regions on opposing sides of each of the two gate structures;
forming at least one shallow trench isolation structure perpendicular to and positioned between and contacting the source/drain regions between adjacent sides of the two gate structures; and
forming a polysilicon layer under the source/drain regions of each of the two gate structures, which includes a portion contacting the at least one shallow trench isolation structure,
wherein the at least one shallow trench isolation structure is between the two gate structures, and
wherein the at least one shallow trench isolation structure comprises multiple shallow trench isolation structures, the multiple isolation structures comprise a first isolation structure positioned between the two gate structures and second isolation structures on sides of the two gate structures opposing the first isolation structure, each of which are contacting the polysilicon layer, and
wherein the at least one shallow trench isolation structure extends deeper into the substrate material than the source/drain regions, and the portion of the polysilicon layer extends upward toward a surface of the underlying substrate material and in combination with remaining portions of polysilicon layer forms a T-shape.